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Teradyne Users Group

TUGx Global Seminars are a series of one day events held throughout the world. These local seminars provide an avenue for Teradyne to share best practices and new test methodologies, ensuring content is relevant to the local audience and empowering our customers to get the most out of their Teradyne technology.

TUGx 2025 Locations & Dates

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United States

  • Austin, TX – Mar 25, 2025
  • Irvine, CA – Mar 6, 2025
  • Plano/Dallas, TX – Mar 27, 2025
  • Salem, NH – Apr 3, 2025
  • San Diego, CA – Mar 4, 2025
  • San Jose, CA – Apr 15, 2025

Europe

  • Catania, Italy – Mar 20, 2025
  • Munich, Germany – Feb 27, 2025
  • Rousset, France – Mar 18, 2025

Asia

  • Alabang, Philippines – Apr 24, 2025
  • Beijing, China – Apr 22, 2025
  • Binyamina, Israel – Feb 20, 2025
  • Hsinchu, Taiwan – Apr 15, 2025
  • Penang, Malaysia – Apr 10, 2025
  • Seoul, Korea – Feb 13, 2025
  • Shanghai, China – Apr 18, 2025
  • ShenZhen, China – Apr 24, 2025
  • Singapore – Apr 8, 2025
  • Yokohama, Japan – Feb 26, 2025

Locations & Details

Times shown are local times
Abstracts

US | Irvine CA

In PersonMarch 6 | Irvine, CA | Track A
8:30 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda
10:00 am
Break
10:15 am
DesignLink: Streamlining Test Pattern Deployment with Automated Solutions
10:45 am
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
11:15 am
MyInfo Copilot: Elevating Information Retrieval
11:45 am
Git and IG-Link: The Dynamic Duo for Unified Programs
12:15 pm
Lunch
1:15 pm
IG-Correlate and STDFStats Toolset Feature Updates
1:45 pm
Bringing Modulated UWB Testing to the UltraFLEXplus via UltraWaveLX0UWB+
2:15 pm
Turning Your UltraWave8G or UltraWave24G into a Spectrum Analyzer
2:45 pm
AI at the Edge: Lessons Learned and Best Practiced (PhD not required) on the UltraEdge2000
3:15 pm
Break
3:30 pm
UltraPort: Enabling High Speed IO Scan on the UltraFLEXplus
4:00 pm
Converting a Test Program to the UltraFLEXplus: A Field Guide
4:30 pm
An Introduction to Tags in IGXL
5:00 pm
Cocktail Reception
In PersonMarch 6 | Irvine, CA | Track B
8:30 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda
10:00 am
Break
10:15 am
DesignLink: Streamlining Test Pattern Deployment with Automated Solutions
10:45 am
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
11:15 am
MyInfo Copilot: Elevating Information Retrieval
11:45 am
Git and IG-Link: The Dynamic Duo for Unified Programs
12:15 pm
Lunch
1:15 pm
Testing Advantages of Implementation of Streaming Scan Network On Chip
1:45 pm
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
2:15 pm
Lessons Learned Running Linux-based Mission Mode Tests on UltraFLEXplus UltraPort and SLT
2:45 pm
3:15 pm
Break
3:30 pm
Managing High Probe Force Applications at Wafer Test on the UltraFLEXplus
4:00 pm
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
5:00 pm
Cocktail Reception

US | Plano/Dallas TX

In PersonMarch 27 | Plano/Dallas, TX | IG-XL Track
8:00 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda
9:15 am
Roadmap
9:45 am
Teradyne Marketing
10:15 am
Break
10:30 am
MyInfo Copilot: Elevating Information Retrieval
11:00 am
Defect Wafer Map Detection
11:30 am
Setup, Implementation, and Benefits of the RCM (Remote Connectivity Matrix)
12:00 pm
Lunch
1:00 pm
The Benefit of Using Design Patterns for C# Programming in IG-XL
1:30 pm
Anatomy of a C# Test Method
2:00 pm
How to Reduce Development Time by 50% Using Displined Deployment of Best Practice Methodologies
2:30 pm
Git and IG-Link: The Dynamic Duo for Unified Programs
3:00 pm
Break
3:15 pm
An Introduction to Tags in IGXL
3:45 pm
Using Functional Vector Compression to Optimize Vector Memory Usage
4:15 pm
The Power of the .NET Ecosystem
4:45 pm
Closing
5:00 pm
Networking Event
In PersonMarch 27 | Plano/Dallas, TX | ETS Track
8:00 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda
9:15 am
Roadmap
9:45 am
Teradyne Marketing
10:15 am
Break
10:30 am
MyInfo Copilot: Elevating Information Retrieval
11:00 am
Defect Wafer Map Detection
11:30 am
Setup, Implementation, and Benefits of the RCM (Remote Connectivity Matrix)
12:00 pm
Lunch
1:00 pm
BMX Dib Extension for improved BMS test accuracy
1:30 pm
MST Protocol Programming – Now Powered by PortBridge!
2:00 pm
Convert2ETS800: The Fast Way of Converting from ETS-364 to ETS-800
2:30 pm
How to Maximize Value on the UPD-64
3:00 pm
Break
3:15 pm
Efficient Awg Pattern creation using SupportCodes MFLApp RampsLoader
3:45 pm
A Users Guide to ETS-800 Sector Coordination
4:15 pm
Weaving the RUG: A Structured, Test Specification Driven Process to Create ETS-800 DIB Concept Block Diagrams
4:45 pm
Closing
5:00 pm
Networking Event

US | Salem NH

In PersonApril 3 | Salem, NH | ETS Track
8:30 am
Registration
9:15 am
Welcome/Opening Remarks/Agenda/Roadmap
10:15 am
Break
10:30 am
Convert2ETS800: The Fast Way of Converting from ETS-364 to ETS-800
11:00 am
Weaving the RUG: A Structured, Test Specification Driven Process to Create ETS-800 DIB Concept Block Diagrams
11:30 am
Setup, Implementation, and Benefits of the RCM (Remote Connectivity Matrix)
12:00 pm
Lunch
1:00 pm
How to Maximize Value on the UPD-64
1:30 pm
BMX Dib Extension for improved BMS test accuracy
2:00 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
2:30 pm
3:00 pm
Break
3:15 pm
MST Protocol Programming – Now Powered by PortBridge!
3:45 pm
DIB Design Techniques for Higher Voltage and Lower Partial Discharge
4:15 pm
Adding SPI Peripherals to the DIB
4:45 pm
Reception
In PersonApril 3 | Salem, NH | UltraFLEX Family Track
8:30 am
Registration
9:15 am
Welcome/Opening Remarks/Agenda/Roadmap
10:15 am
Break
10:30 am
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
11:00 am
UltraFLEXplus Towerless Hinge Test Cell Solution Using Outer Pull Down (OPD) Docking
11:30 am
AI at the Edge: Lessons Learned and Best Practiced (PhD not required) on the UltraEdge2000
12:00 pm
Lunch
1:00 pm
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
1:30 pm
Anatomy of a C# Test Method
2:00 pm
MyInfo Copilot: Elevating Information Retrieval
2:30 pm
Support Multiple Test Platforms via Tester Abstraction Layers
3:00 pm
Break
3:15 pm
Converting a Test Program to the UltraFLEXplus: A Field Guide
3:45 pm
Using the PinPMU Pattern Synchronized Ramping Feature on UltraFLEXplus Testing Low Cost MCUs at High Site Counts
4:15 pm
Testing Wireless Battery Management Devices on the UltraFLEXplus
4:45 pm
Reception

US | San Diego CA

In PersonMarch 4 | San Diego, CA | Machine Learning/IGXL Tools Track
8:30 am
An Introduction to Tags in IGXL
Registration
9:00 am
Welcome/Opening Remarks/Agenda/Roadmap
10:00 am
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
10:30 am
Break
10:45 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
11:15 am
Support Multiple Test Platforms via Tester Abstraction Layers
11:45 am
DesignLink: Streamlining Test Pattern Deployment with Automated Solutions
12:15 pm
Lunch
1:15 pm
UltraEdge2000 – AI at the Edge – Multisite implementation and considerations (PhD still not required)
1:45 pm
Using Machine Learning to Detect Patterns on Wafermaps
2:15 pm
Converting a Test Program to the UltraFLEXplus: A Field Guide
2:45 pm
Understanding of PACE Pipeline Stall & Full Speed
3:15 pm
Break
3:30 pm
An Introduction to Tags in IGXL
4:00 pm
IG-Correlate and STDFStats Toolset Feature Updates
4:30 pm
MyInfo Copilot: Elevating Information Retrieval
5:00 pm
Reception
In PersonMarch 4 | San Diego, CA | RF/.Net Track
8:30 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda/Roadmap
10:00 am
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
10:30 am
Break
10:45 am
Testing Your PA Using DPD and UltraWave8G
11:15 am
How the UltraFLEXplus Enables High Bandwidth IQ Test by UltraPAC500
11:45 am
V-band and E-band Testing on the UltraFLEXplus. A Near DUT Experience.
12:15 pm
Lunch
1:15 pm
The Power of the .NET Ecosystem
1:45 pm
2:15 pm
The Benefit of Using Design Patterns for C# Programming in IG-XL
2:45 pm
Anatomy of a C# Test Method
3:15 pm
Break
3:30 pm
Best Practice for DevOps (Oasis and IG-Correlate) Used in Actual Project
4:00 pm
Git and IG-Link: The Dynamic Duo for Unified Programs
4:30 pm
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
5:00 pm
Reception

US | San Jose CA

In PersonApril 15 | San Jose, CA | ETS Track
8:30 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda/Roadmap
10:00 am
Break
10:15 am
Convert2ETS800: The Fast Way of Converting from ETS-364 to ETS-800
10:45 am
A Users Guide to ETS-800 Sector Coordination
11:15 am
MST Protocol Programming – Now Powered by PortBridge!
11:45 am
Lunch
1:30 pm
Setup, Implementation, and Benefits of the RCM (Remote Connectivity Matrix)
2:00 pm
Adding SPI Peripherals to the DIB
2:30 pm
Break
2:45 pm
ETS-88 & 364: Analog Resource Control via Digital Resource Features (PSQ Pattern Sequencer Signals & Paths)
3:15 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
3:45 pm
How to Maximize Value on the UPD-64
4:15 pm
BMX Dib Extension for improved BMS test accuracy
4:45 pm
Reception
In PersonApril 15 | San Jose, CA | UltraFLEX/UltraFLEXplus/IGXL Track
8:30 am
Registration
9:00 am
Welcome/Opening Remarks/Agenda/Roadmap
10:00 am
Break
10:15 am
Lessons Learned Running Linux-based Mission Mode Tests on UltraFLEXplus UltraPort and SLT
10:45 am
UltraPort: Enabling High Speed IO Scan on the UltraFLEXplus
11:15 am
How the UltraFLEXplus Enables High Bandwidth IQ Test by UltraPAC500
11:45 am
Lunch
1:30 pm
Bringing Modulated UWB Testing to the UltraFLEXplus via UltraWaveLX0UWB+
2:00 pm
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
2:30 pm
Break
2:45 pm
AI at the Edge: Lessons Learned and Best Practiced (PhD not required) on the UltraEdge2000
3:15 pm
Support Multiple Test Platforms via Tester Abstraction Layers
3:45 pm
Git and IG-Link: The Dynamic Duo for Unified Programs
4:15 pm
4:45 pm
Reception

Germany | Munich

In PersonFebruary 27 | Munich, Germany | UltraFLEX Family Track
8:00 am
Registration
9:00 am
Welcome & Business Update
9:15 am
Teradyne Product and Capability Roadmap
9:45 am
Automotive Imaging Radar Device Testing on UltraFLEXplus Test Platform with the DX81, 76-81GHz Modules
10:15 am
Break
10:30 am
Synopsys Streaming Fabric Support on UltraFLEX Family
11:00 am
MyInfo Copilot: Elevating Information Retrieval
11:30 am
How to Reduce Development Time by 50% Using Displined Deployment of Best Practice Methodologies
12:00 pm
Lunch
1:00 pm
The Power of the .NET Ecosystem
1:30 pm
Test Program Profiling Under .Net
2:00 pm
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
2:30 pm
Break
3:00 pm
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
3:30 pm
Using the PinPMU Pattern Synchronized Ramping Feature on UltraFLEXplus Testing Low Cost MCUs at High Site Counts
4:00 pm
Bringing Modulated UWB Testing to the UltraFLEXplus via UltraWaveLX0UWB+
4:30 pm
Wrap-Up & Closing Remarks
4:45 pm
Networking Event
In PersonFebruary 27 | Munich, Germany | ETS Track
8:00 am
Registration
9:00 am
Welcome & Business Update
9:15 am
Teradyne Product and Capability Roadmap
9:45 am
Automotive Imaging Radar Device Testing on UltraFLEXplus Test Platform with the DX81, 76-81GHz Modules
10:15 am
Break
10:30 am
Synopsys Streaming Fabric Support on UltraFLEX Family
11:00 am
MyInfo Copilot: Elevating Information Retrieval
11:30 am
How to Reduce Development Time by 50% Using Displined Deployment of Best Practice Methodologies
12:00 pm
Lunch
1:00 pm
MST Protocol Programming – Now Powered by PortBridge!
1:30 pm
Weaving the RUG: A Structured, Test Specification Driven Process to Create ETS-800 DIB Concept Block Diagrams
2:00 pm
SiC MOSFET Testing in ETS88Duo DP32 Solution
2:30 pm
Break
3:00 pm
Improving Throughput with Microcontroller Based Concurrent Testing on Any Teradyne Test Platform
3:30 pm
How to Maximize Value on the UPD-64
4:00 pm
BMX Dib Extension for improved BMS test accuracy
4:30 pm
Wrap-Up & Closing Remarks
4:45 pm
Networking Event

France | Rousset

In PersonMarch 18 | Rousset, France | UltraFLEX/UltraFLEXplus Track
9:00 am
Registration
9:30 am
TUGx Opening
9:40 am
HW and SW Roadmap
10:30 am
Break
10:45 am
Accelerating AI Innovation through Strategic Academic-Industry Collaboration
11:15 am
UltraEdge2000 – AI at the Edge – Multisite implementation and considerations (PhD still not required)
11:45 am
MyInfo Copilot: Elevating Information Retrieval
12:15 pm
Agnostic GPIB Emulation for Teradyne Testers: Streamlining Production and Testing Processes
1:45 pm
Measuring the Input Capacitance of the Differential Pins of the NFC's Antenna
2:15 pm
How to Reduce Development Time by 50% Using Displined Deployment of Best Practice Methodologies
2:45 pm
Rapid Prototyping On UltraFLEX Training DIB Strips
3:15 pm
Break
3:30 pm
4:00 pm
Anatomy of a C# Test Method
4:30 pm
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
5:00 pm
Wrap-Up
In PersonMarch 18 | Rousset, France | Imagers Track
9:00 am
Registration
9:30 am
TUGx Opening
9:40 am
HW and SW Roadmap
10:30 am
Break
10:45 am
Accelerating AI Innovation through Strategic Academic-Industry Collaboration
11:15 am
UltraEdge2000 – AI at the Edge – Multisite implementation and considerations (PhD still not required)
11:45 am
MyInfo Copilot: Elevating Information Retrieval
12:15 pm
Agnostic GPIB Emulation for Teradyne Testers: Streamlining Production and Testing Processes
1:45 pm
Imaging DSP Power Calculation
2:15 pm
Imaging File Transfer
2:45 pm
ICMCD Instrument
3:15 pm
Break
3:30 pm
MIPI D-PHY Testing by Direct Capture Using DSSC Digital Capture with UltraPin2200 on the UltraFLEXplus
4:00 pm
IP750 SiPMs Test Solution
4:30 pm
IG-Correlate and STDFStats Toolset Feature Updates
5:00 pm
Wrap-Up
In PersonMarch 18 | Rousset, France | High Complexity Digital Track
9:00 am
Registration
9:30 am
TUGx Opening
9:40 am
HW and SW Roadmap
10:30 am
Break
10:45 am
Accelerating AI Innovation through Strategic Academic-Industry Collaboration
11:15 am
UltraEdge2000 – AI at the Edge – Multisite implementation and considerations (PhD still not required)
11:45 am
MyInfo Copilot: Elevating Information Retrieval
12:15 pm
Agnostic GPIB Emulation for Teradyne Testers: Streamlining Production and Testing Processes
1:45 pm
Synopsys Streaming Fabric Support on UltraFLEX Family
2:15 pm
Timing Search and Alignment for SSN on UltraFLEXplus
2:45 pm
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
3:15 pm
Break
3:30 pm
Testing Advantages of Implementation of Streaming Scan Network On Chip
4:00 pm
DesignLink: Streamlining Test Pattern Deployment with Automated Solutions
4:30 pm
ScanFalcon: A Custom Data Consumer for IG-XL
5:00 pm
Wrap-Up

Philippines | Alabang

In PersonApril 24 | Alabang, Philippines
9:00 am
Registration
9:30 am
Introduction
9:35 am
Opening Video
9:40 am
Welcome/Opening Remarks/Agenda
9:50 am
Device Testing Trends and Teradyne’s Product Roadmap
11:05 am
Break
11:20 am
Convert2ETS800: The Fast Way of Converting from ETS-364 to ETS-800
11:50 am
Introduction to AI Chip Testing Solution Based on UltraFLEXplus
12:20 pm
Quiz Session
12:25 pm
Lunch
1:55 pm
The Power of the .NET Ecosystem
2:25 pm
ETS-88 & 364: Analog Resource Control via Digital Resource Features (PSQ Pattern Sequencer Signals & Paths)
2:55 pm
A Users Guide to ETS-800 Sector Coordination
3:25 pm
Quiz Session
3:30 pm
Break
3:45 pm
Enhance Equipment Efficiency and Throughput Through Teradyne's Multi Sector Technology SW
4:15 pm
Creating Your First DSSC Parking Loop: Step-by-Step Instructions
4:45 pm
Quiz Session
4:50 pm
Final Q&A Session

Israel | Binyamina

In PersonFebruary 20 | Binyamina, Israel
8:00 am
Registration
9:00 am
Welcome
9:15 am
Teradyne Product and Capability Roadmap
10:15 am
The Power of the .NET Ecosystem
10:45 am
Break
11:00 am
How to Reduce Development Time by 50% Using Displined Deployment of Best Practice Methodologies
11:30 am
Testing Advantages of Implementation of Streaming Scan Network On Chip
12:00 pm
Proactively Control DUT’s Temperature
1:30 pm
MyInfo Copilot: Elevating Information Retrieval
2:00 pm
Lunch
3:00 pm
Networking Event

Malaysia | Penang

In PersonApril 10 | Penang, Malaysia
9:00 am
Registration
9:30 am
Introduction
9:35 am
Opening Video
9:40 am
Welcome/Opening Remarks/Agenda
9:50 am
Device Testing Trends and Teradyne’s Product Roadmap
11:05 am
Break
11:20 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
11:50 am
Introduction to AI Chip Testing Solution Based on UltraFLEXplus
12:20 pm
Quiz Session
12:25 pm
Lunch
1:55 pm
The Power of the .NET Ecosystem
2:25 pm
SiC MOSFET Testing in ETS88Duo DP32 Solution
2:55 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
3:25 pm
Quiz Session
3:30 pm
Break
3:45 pm
Improving Time to Market Using ETS-800 Productivity Tools During Test Development
4:15 pm
Enhance Equipment Efficiency and Throughput Through Teradyne's Multi Sector Technology SW
4:45 pm
Quiz Session
4:50 pm
Final Q&A Session

Korea | Seoul

In PersonFebruary 13 | Seoul, Korea | RF & CIS Track
9:00 am
Registration
9:15 am
Welcome/Opening Remarks/Agenda
9:30 am
Keynote Speech: Memory Device Integrated with SOC Device
10:00 am
Device Testing Trends & Teradyne Roadmap
11:00 am
Break
11:15 am
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
11:45 am
IP750 SiPMs Test Solution
12:15 pm
Lunch
1:15 pm
MIPI D-PHY Testing by Direct Capture Using DSSC Digital Capture with UltraPin2200 on the UltraFLEXplus
1:45 pm
Testing Wireless Battery Management Devices on the UltraFLEXplus
2:15 pm
Break
2:30 pm
Bringing Modulated UWB Testing to the UltraFLEXplus via UltraWaveLX0UWB+
3:00 pm
RF Customized Library for Time Saving of Test Program Development and Test Time Reduction
3:30 pm
Turning Your UltraWave8G or UltraWave24G into a Spectrum Analyzer
4:00 pm
Break
4:15 pm
Wrap-Up
In PersonFebruary 13 | Seoul, Korea | Discrete/Production Support Track
9:00 am
Registration
9:15 am
Welcome/Opening Remarks/Agenda
9:30 am
Keynote Speech: Memory Device Integrated with SOC Device
10:00 am
Device Testing Trends & Teradyne Roadmap
11:00 am
Break
11:15 am
Agnostic GPIB Emulation for Teradyne Testers: Streamlining Production and Testing Processes
11:45 am
BMX Dib Extension for improved BMS test accuracy
12:15 pm
Lunch
1:15 pm
Wafer Level Burn In for SiC Power Devices
1:45 pm
Using GreenPAK for Low-cost, Flexible and Fast Failure Prevention Circuit
2:15 pm
Break
2:30 pm
SiC MOSFET Testing in ETS88Duo DP32 Solution
3:00 pm
External Switching Buffer Module for HVMU 2.0 Direct Path
3:30 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
4:00 pm
Break
4:15 pm
Wrap-Up
In PersonFebruary 13 | Seoul, Korea | SOC Track
9:00 am
Registration
9:15 am
Welcome/Opening Remarks/Agenda
9:30 am
Keynote Speech: Memory Device Integrated with SOC Device
10:00 am
Device Testing Trends & Teradyne Roadmap
11:00 am
Break
11:15 am
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
11:45 am
Anatomy of a C# Test Method
12:15 pm
Lunch
1:15 pm
UltraPort: Enabling High Speed IO Scan on the UltraFLEXplus
1:45 pm
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
2:15 pm
Break
2:30 pm
AI at the Edge: Lessons Learned and Best Practiced (PhD not required) on the UltraEdge2000
3:00 pm
IG-Correlate and STDFStats Toolset Feature Updates
3:30 pm
MyInfo Copilot: Elevating Information Retrieval
4:00 pm
Break
4:15 pm
Wrap-Up

China | Shanghai

In PersonApril 18 | Shanghai, China | RF and Mixed-Signal Track
9:00 am
Registration
9:30 am
Opening Remarks
9:35 am
Product Roadmap
10:20 am
Break
10:30 am
Optimizing AP Chip Testing on UltraFLEXplus: Strategies for Enhanced Performance and Cost Efficiency
11:00 am
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
11:30 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
12:00 pm
Lunch
1:30 pm
Using TRV Proving High Performance of UW8G Single-Source-MultiTone(SSMT) Feature
2:00 pm
Concurrent Test Performance on UltraFLEXplus in Practical Project
2:30 pm
Break
2:45 pm
Bringing Modulated UWB Testing to the UltraFLEXplus via UltraWaveLX0UWB+
3:15 pm
How the UltraFLEXplus Enables High Bandwidth IQ Test by UltraPAC500
3:45 pm
Best Practice for DevOps (Oasis and IG-Correlate) Used in Actual Project
4:15 pm
Closing
In PersonApril 18 | Shanghai, China | ETS Track
9:00 am
Registration
9:30 am
Opening Remarks
9:35 am
Product Roadmap
10:20 am
Break
10:30 am
Optimizing AP Chip Testing on UltraFLEXplus: Strategies for Enhanced Performance and Cost Efficiency
11:00 am
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
11:30 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
12:00 pm
Lunch
1:30 pm
SiC MOSFET Testing in ETS88Duo DP32 Solution
2:00 pm
Protocol Testing Solution Based on ETS-88
2:30 pm
Break
2:45 pm
How to Enhance Accuracy in High-Resolution ADC and DAC Testing
3:15 pm
Wafer Level Burn In for SiC Power Devices
3:45 pm
How to Use the DSSC Operational Modes for Multi-site Testing Efficiently
4:15 pm
Closing
In PersonApril 18 | Shanghai, China | Digital and Tools Track
9:00 am
Registration
9:30 am
Opening Remarks
9:35 am
Product Roadmap
10:20 am
Break
10:30 am
Optimizing AP Chip Testing on UltraFLEXplus: Strategies for Enhanced Performance and Cost Efficiency
11:00 am
An Innovative Solution for Fully Testing High Speed Serial Interfaces to 112Gbps and Beyond
11:30 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
12:00 pm
Lunch
1:30 pm
How the EFA (Electric Failure Analysis) Works on Streaming Scan Network Patterns
2:00 pm
How to Use PortBridge's Register Map Integration to Simplify Test Development and Debug
2:30 pm
Break
2:45 pm
High Efficiency Fail Log Capture and Analysis Solution on UltraFLEXplus
3:15 pm
Introduction to AI Chip Testing Solution Based on UltraFLEXplus
3:45 pm
The Best Practice of Program Auto-gen and Audit
4:15 pm
Closing

Singapore

In PersonApril 8 | Singapore
9:00 am
Registration
9:30 am
Introduction
9:35 am
Opening Video
9:40 am
Welcome/Opening Remarks/Agenda
9:50 am
Device Testing Trends and Teradyne’s Product Roadmap
11:00 am
Break
11:15 am
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
11:45 am
Introduction to AI Chip Testing Solution Based on UltraFLEXplus
12:15 pm
Best Practice for DevOps (Oasis and IG-Correlate) Used in Actual Project
12:45 pm
Quiz Session
12:50 pm
Lunch
2:20 pm
The Power of the .NET Ecosystem
2:50 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
3:20 pm
Converting a Test Program to the UltraFLEXplus: A Field Guide
3:50 pm
Quiz Session
3:55 pm
Break
4:10 pm
Enhance Equipment Efficiency and Throughput Through Teradyne's Multi Sector Technology SW
4:40 pm
Quiz Session
4:45 pm
Final Q&A Session

Japan | Yokohama

In PersonFebruary 26 | Yokohama, Japan | IGXL Track
10:00 am
Welcome/Business update from FOM/RSM
10:30 am
Device Trends and Roadmap
11:30 am
Break
11:45 am
Lessons Learned Running Linux-based Mission Mode Tests on UltraFLEXplus UltraPort and SLT
12:15 pm
Using Machine Learning to Detect Patterns on Wafermaps
12:45 pm
Break
1:35 pm
Improving the efficiency of device test development using software tools
2:05 pm
Testing Wireless Battery Management Devices on the UltraFLEXplus
2:35 pm
Break
2:55 pm
Using the PinPMU Pattern Synchronized Ramping Feature on UltraFLEXplus Testing Low Cost MCUs at High Site Counts
3:25 pm
ICMCD Instrument
3:55 pm
Break
4:05 pm
A Successful Journey of SSN Implementation in Multi-Die Chiplet Packaging for Network Processor
4:35 pm
Collecting Scan Fails, What's Next? Introduction to Diagnosis
5:05 pm
Break
5:25 pm
Networking Event
7:00 pm
Closing
In PersonFebruary 26 | Yokohama, Japan | ETS Track
10:00 am
Welcome/Business update from FOM/RSM
10:30 am
Device Trends and Roadmap
11:30 am
Break
11:45 am
Lessons Learned Running Linux-based Mission Mode Tests on UltraFLEXplus UltraPort and SLT
12:15 pm
Using Machine Learning to Detect Patterns on Wafermaps
12:45 pm
Break
1:35 pm
Improving the efficiency of device test development using software tools
2:05 pm
Testing Wireless Battery Management Devices on the UltraFLEXplus
2:35 pm
Break
2:55 pm
BMX Dib Extension for improved BMS test accuracy
3:25 pm
MST Protocol Programming – Now Powered by PortBridge!
3:55 pm
Break
4:05 pm
Partial Discharge Testing, ETS-88 UHV (Ultra High Voltage) Testing
4:05 pm
DIB Design Techniques for Higher Voltage and Lower Partial Discharge
4:35 pm
Using GreenPAK for Low-cost, Flexible and Fast Failure Prevention Circuit
5:05 pm
Break
5:25 pm
Networking Event
7:00 pm
Closing

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