Scan testing has gotten faster since customers have added SSN (Streaming Scan Network) to the design. In the past, scan testing was usually at 100MHz, but it has evolved to the highest speed of 400MHz now. Relatively, the overall timing error that can be accommodated becomes smaller. In the past, the timing was usually set fixed in the program. However, the manufacturing processes, voltage conditions, etc. may make device have some difference and then test failures and loss yield, so the timing setting becomes very important. In the past, characterization was used for timing adjustment, but characterization is relatively time-consuming in search, because the pattern requires repeated bursts, and the application result is also complex. For the problem of timing alignment in high-speed digital testing, UFplus provides new functions AutoStrobe and Edge Offset which can quickly calibrate and apply timing during the test process. It would be a more efficient solution than traditional characterization. Therefore, in this paper, we will demonstrate the benefits of this technology through an actual MediaTek project.