Using Machine Learning to Detect Patterns on Wafermaps
Original Author: Andres Pineda
Andres Pineda is a factory applications engineer for the power discrete unit at Teradyne, where he is responsible for design analog and digital interfaces to implement switching, filtering, signal conversion, and other functions. Prior to Teradyne, Andres was a schematic and layout designer at Intel. He holds a bachelor degree in electronic engineering from Tecnologico of Costa Rica, he also holds a master degree on business administration from the ENAE and a master degree in Project Management from the Tecnologico de Costa Rica.
Integration circuit (IC) fabrication is very complicated, as many manufacturing steps have to be executed on the same wafer. All fabrication steps are subject to errors, wafer defect patterns are the results of various problems in the fabrication and wafer test process. Thus, the wafer map defect patterns can be used to identify sources of errors in the manufacturing process.
Recently, local defect pattern recognition has attracted a lot of research interests. The results of wafer test are usually presented in a wafer map, which gives locations of failed dies in a wafer.
There is plenty information of Machine learning and wafer map recognition patterns on published research, the idea of this paper and project is to use this information as leverage to create a pattern recognition system for Teradyne tool MST, that will detect patterns automatically when running production on the clients' sites. This will give added value to our services and will help our clients to recognize manufacturing issues quickly.
Improving Test Code Quality Using IG-XL .NET
Original Author: Steve Shirk
Steve Shirk is the product owner of .NET Development in IG-XL, where he is responsible for defining the product requirements. Previously at Teradyne, he has worked in the Systems Engineering, Core Software, and Applications groups. He holds a Bachelor of Science in Computer Systems Engineering from Rensselaer Polytechnic Institute.
Using capabilities that exist in the .NET Framework, as well as additional functionality provided with IG-XL, users have the ability to improve the test coverage they are able to achieve in their test libraries, as well as measure the coverage. A mocking framework is provided that enables users to test code without IG-XL even installed. This enables testing paths through the code where it is easiest and fastest to test the code. The next stage of testing is to test the library code integrated with IG-XL, with the new response DB capability. Users can ensure that their library code behaves as expected, based on specified tester responses. Finally, test program flows and binning can be tested with the response DB to ensure the quality of the production test program flows.
Convert2ETS800: The Fast Way of Converting from ETS-364 to ETS-800
Original Author: Massimo Zambusi
Massimo Zambusi is a factory applications Engineer at Teradyne, where he is responsible for Productivity Tools and Field support on Flex and ETS-800 platforms. Prior to this role, Massimo was the Automotive Expert Community Leader and Field Applications Engineer. He holds a degree in Electronics Engineering from Politecnico di Milano - Italy.
Co-Author: Alice Hu
Alice Hu is the factory application engineer for productivity tools developing at Teradyne, where she is responsible for developing various productivity tools for the UltraFLEX or Eagle testers. She holds a degree in Master from Harbin Institute of Technology.
ETS-364 is a top runner platform at many customers for decades. ETS-800 is the high site count evolution, which offers a tremendous boost in throughput and Cost Of Test. Despite the two platforms having similar instrumentation, the multisite solution on ETS-800 is seldom a copy of the ETS-364 test concept, as the native ETS-800 resources and APEx are the key enablers. Porting applications to ETS-800 requires converting the Visual Studio project from VS2005 to a modern version, the EV project into EV-MST, the project structure into ETS-800 syntax. This also requires the user to map legacy resources to new ones (like UPD-64); APEx and DIB HW connections need to be considered when updating the code. The user will want to convert the analog resource patterns (AWG) into the new resource syntax. The digital vector EVD has to be converted into eDST WKBK, and all the timings and levels context have to be properly translated and merged into eDST profiles. The Teradyne Convert2ETS800 Productivity Tool makes all this easy and fast! Convert2ETS800 = Ease of Use + Time To Market.
The Benefit of Using Design Patterns for C# Programming in IG-XL
Original Author: Blake Wang
Blake Wang is the field application engineer for test program development at Teradyne, where he is responsible for C# transition and development of RF projects for the UltraFLEX/UltraFLEXplus tester. Prior to Teradyne, Blake was the software engineer at Foxconn Technology Group. He holds a Master of Science in computer science from National Taiwan University of Science and Technology.
Before IG-XL 10.40, VBA is more of a scripting tool in IG-XL for test program development. As the test codes are growing larger, those Legacy Codes are hard to maintain or may become unreadable. It may take hard work to add a brand-new test code or refactor the whole test program. C# is now the new supporting language in IG-XL test program development after IGXL 10.40.10. Compared with VBA, C# is a powerful and versatile object-oriented programming language that has become an essential tool for software development on .NET platform, so we can use the features (inheritance, overriding, overloading…etc.) of OO programming in IG-XL test program development to let test codes more readable and structured. Design Pattern is another tool that is used to solve the problems of Object Generation and Integration when moving to object-oriented programming. In this paper, we will introduce some Design patterns that can be used in IG-XL test program development. Singleton Pattern could solve the object generation problem and reduce unnecessary memory usage. Adapted Pattern simplified the structure of each Test Method in IG-XL. The Factory Pattern the complex test items or large data to be more organized. The implementation of Design Pattern might let IG-XL program develop more efficiently and developing.
Introduction to AI Chip Testing Solution Based on UltraFLEXplus
Original Author: Vincent Zhang
Vincent Zhang is the field applications team leader for SOC/Analog/RF devices at Teradyne, where he is responsible for provide different application solutions on UltraFLEXplus/UltraFLEX/J750 platform for China local emerging customers. Prior to Teradyne, Vincent was responsible for HW calibration/verification solution at Litepoint. He holds a Master degree of Electronics & Communications from ZheJiang University.
Co-Author: Troy Zhang, Nancy-Na Chen & Yuxin Song
Troy Zhang is a factory application engineer for digital and software tools group at Teradyne, where he is responsible for high-speed digital test solution development and supporting Asia Design-Ins. Prior to this role, Troy was the field application engineer at SEG China. He holds a Master of Science degree in Precision Instrument Engineering from Shanghai Jiao-Tong University.
Nancy-Na Chen is Field application engineer at Teradyne, has been worked at Teradyne for 15 years. has good eKnowledge with J750, UltraFLEX and UltraFLEXplus. She holds a bachelor's degree in Electronic Information Engineering from Anhui University.
With the rapid development of artificial intelligence technology, AI chips have become the core hardware driving progress in this field. However, accurately assessing the performance of AI chips and implementing efficient grading is a key issue faced by current ATE testing. This article aims to introduce an AI chip testing solution based on the UltraFLEXplus (UFP) platform, discussing its application in functional implementation, Partial Good grading strategy, and thermal management. Firstly, the article will briefly introduce the universal testing solutions for CPU/GPU/AI chips implemented on the UFP testing platform, including traditional Process-Voltage-Temperature (PVT) analysis, Physical Layer testing (PHY), Scan testing (SCAN), and Memory Repair (MR). Subsequently, considering the grading requirements of AI chips that necessitate a comprehensive consideration of computing speed, memory bandwidth, power consumption, application scenarios, scalability, and other specific functions, this article will focus on introducing a multi-site, systematic testing and grading method based on UFP. A demo program will illustrate the process of Partial Good grading to readers. Lastly, in view of the high current issues that AI chips may encounter during testing, the final part of this article will explore the design of thermal management and current monitoring schemes. This includes over-temperature protection mechanisms, simultaneous profiling functions for voltage & current, and the design of current monitoring circuits for core power supplies. In summary, the AI chip testing solution based on UFP proposed in this article enhances testing efficiency and accuracy. The discussions on thermal management and current monitoring provide strong support to ensure reliability and stability during the ATE process.
AI at the Edge: Lessons Learned and Best Practiced (PhD not required) on the UltraEdge2000
Original Author: Keith Lucy
Keith Lucy has been with Teradyne since 1998 and has mixed signal and high speed digital experience on numerous testers from the A567 to the UltraFLEXplus. He was part of the applications development team that was responsible for the initial bring up of the UltraFLEX platform. Prior to Teradyne, he spent 11 years with Raytheon after graduating From Norwich University in 1986 with a BS in EE. He is currently based in North Reading where he splits his time between the Field Support team in San Diego and the Strategic Applications / Software Solutions group in North Reading.
At the core of Teradyne’s Analytic Management Platform (AMP) is the UltraEdge2000 server, capable of executing Machine Learning models during device test. When moving any software solution from development to production deployment, real world possibilities must be considered. This paper will discuss lessons learned and best practices to be followed when developing and deploying machine learning models on UltraEdge2000 from an IG-XL test program. Topics to be covered include – Deployment methods - Docker or XAR, which is best and when? Communication methods – Sockets or FIFOs? Adapting to testers that do not have UltraEdge hardware or libraries Best practices for server applications developers.
Best Practice for DevOps (Oasis and IG-Correlate) Used in Actual Project
Original Author: Ze Chen
Ze Chen is the factory application engineer for software developing at Teradyne, where he is responsible for developing various software tools for UltraFLEX or Eagle testers. He holds a Bachelor of Integrated Circuit Design and Integrated System from ShanDong University.
This presentation shares use cases of Teradyne DevOps in actual project development, highlighting the use of DevOps to automate manual tasks and enhance the quality and efficiency of the project development process. This project utilizes Teradyne's self-developed DevOps process (DevOpsForTest), which integrates IG-Review, IG-Data, and IG-Correlate to offer solutions to customers. First, the rules of IG-Review are customized based on the customer's inspection specifications, and each rule is graded to assist test engineers in quickly identifying and resolving issues. Furthermore, the TestInsight tool is used to batch convert patterns and merge timings, while IG-Data automatically generates DFT test items. This eliminates the need for complex manual operations, significantly reducing human errors and improving development efficiency. Lastly, IG-Correlate is executed automatically through DevOps to generate customized reports and collect execution results for integrated analysis. This enables test engineers to gain deeper insights into the test results across test runs, instruments, and even platforms. It also provides a solution for achieving site-to-site correlation and lot-to-lot correlation.
UltraEdge2000 – AI at the Edge – Multisite implementation and considerations (PhD still not required)
Original Author: Keith Lucy
Keith Lucy has been with Teradyne since 1998 and has mixed signal and high speed digital experience on numerous testers from the A567 to the UltraFLEXplus. He was part of the applications development team that was responsible for the initial bring up of the UltraFLEX platform. Prior to Teradyne, he spent 11 years with Raytheon after graduating From Norwich University in 1986 with a BS in EE. He is currently based in North Reading where he splits his time between the Field Support team in San Diego and the Strategic Applications / Software Solutions group in North Reading.
At the core of Teradyne’s Analytic Management Platform (AMP) is the UltraEdge2000 server, capable of executing Machine Learning models during device test. A key component to this solution is a transparent multisite use model that matches IG-XL to make it seamlessly integrated into IG-XL. This paper will discuss the multisite implementation of the UltraEdge instrument and best practices to be followed when developing and deploying machine learning models on UltraEdge2000 from an IG-XL test program.
Improving the efficiency of device test development using software tools
Original Author: Rena Mitsugi
Rena Mitsugi is a Field Application Engineer for Image Sensor Devices at Teradyne, where she is responsible for test program development. She holds a degree in Information, Communication, and Electronic Engineering from the National Institute of Technology, Kumamoto College.
In recent years, the complexity of devices being tested has increased significantly. This complexity has become a challenge for developers. Engineers now need more time to develop tests than before. The key to solving this challenge is to optimize the development process and improve efficiency. In my presentation, I will propose a solution that utilizes software tools such as OASIS, MyInfo Copilot, and TRV. These tools provide a way to efficiently proceed with development tasks. By adopting them, customers can shorten time to market and reduce the burden on engineers. For example, MyInfo Copilot is easy to use because engineers can ask questions in their local language, saving time reading extensive help files. In addition, the Oasis tool IG-Link allows engineers to manage programs more modularly. This also allows debugging by multiple people, and by linking with the version control tool (Git), engineers can easily control versions. In addition, Oasis has a wide range of support tools. In addition, IG-XL currently supports programs in .NET. By utilizing third-party tools such as GitHub Copilot in the development environment Visual Studio, engineers can not only improve the quality of their code and save time, but also get new ideas from GitHub Copilot. TRV is a tool that allows users to observe program behavior in real time, eliminating the need to analyze STDF files and allowing users to analyze debug data on the fly. In conclusion, the Teradyne software presented here provides solutions that can reduce engineers' workload. We hope that this presentation will interest customers in these valuable tools and encourage them to adopt them.
Defect Wafer Map Detection
Original Author: Katie Monroe
Katie Monroe is a Machine Learning Engineer for the AI Team at Teradyne, where she is responsible for developing machine learning models and data science algorithms. She holds a Master of Science in Statistics from the University of Virginia.
Co-Author: Jin Yu
Jin Yu is the head of machine learning for semiconductor test division at Teradyne, where Jin is responsible for leading machine learning initiatives to enhance testing processes, product performance, and internal productivity. In the meanwhile Jin is also a part-time faculty at Khoury College of Computer Sciences, Northeastern University. Prior to Teradyne, Jin was the director of machine learning at Sigify/Philips Research. Jin holds a PhD degree in Electrical and Computer Engineering from Stevens Institute of Technology.
Abstract for Defect wafer map detection: Wafer testing is an important step in judging the quality of chips on wafers and plays a crucial role in yield assessment. After wafer testing, the judge information for each chip on one wafer will form a wafer map where 0 denotes out of wafer, 1 denotes PASS and 2 denotes FAIL. The defect patterns on wafer maps are often induced by some issues in the manufacturing process and some patterns keep recurring during the process. Defect wafer map detection aims to detect the wafers with special defect patterns for root cause analysis, which is useful for yield optimization. This work used multiple machine learning strategies. We firstly used a pre-trained model called DINOv2 to convert raw wafer images into image embeddings. Then, using those embeddings, we trained models such as Neural Networks, XGBoost, and LightGBM among which LightGBM reached the best performance. After checking the incorrect predictions, we performed label enhancement on some wrongly labeled wafer maps, leading to a 2% increase in model accuracy. Moreover, we added some symbolic features like yield rate, coordinates of failed mass center and the normalized distance between failed mass center and wafer center onto embeddings for training, which resulted in another 2% increase in model accuracy. Additionally, after looking into the Renesas data, we are working towards redefining some wafer defect patterns for specific products based on their own special defect root cause. Our defect wafer map detector may be used to help process engineers make decisions during the wafer testing process. Keywords – wafer defect map, AI for test, classification, Symbolic AI
Taking Advantage of Teradyne’s Analytic Management Platform for Adaptive Test Strategies
Original Author: Akanksha Wadhwa
Akanksha Wadhwa is a Software Engineer working on Data Analytics Solutions at Teradyne, where she is helping design and implement the new Archimedes Analytics Management Platform. She holds a Bachelor of Science in computer engineering and robotics from the University of Massachusetts, Lowell.
Semiconductor manufacturers seek adaptive test strategies to optimize their test efficiency. To provide adaptive test solutions, test engineers need to link data from the test cell to custom AI/Machine Learning models that can provide a dynamic response to alter the test program execution. Using Teradyne's recently introduced Analytic Management Platform (AMP), this presentation will demonstrate how test engineers can readily create portable customizable solutions that leverage their AI model's knowledge to alter IG-XL test program execution without requiring persistent job changes. We will compare two categories of adaptive changes: changes that can be requested asynchronously, such as disabling tests, and changes that require being done synchronously immediately after a touchdown, such as a rebin operation. A walk-through of a customized rebin solution for IG-XL using the UltraEdge will be covered during the presentation. This presentation will highlight how AMP and its SDK can easily support integration with a wide range of AI and Machine Learning models, enhancing the test engineer’s capability to harness the power of their test data to make real-time decisions that can improve overall test outcomes.
Connect your UltraFLEX to a Universal Robot
Original Author: Christine Soh
Christine Soh is a factory applications engineer for production integration at Teradyne, Singapore, where she is responsible for developing custom software such of user interfaces and drivers with IG-XL and ETS for production support. She holds a Bachelor of Engineering from the Singapore University of Technology and Design.
With the Industrial 4.0 movement, we see more and more advanced digital technologies being produced, and more and more integration of such intelligent technologies into manufacturing and industrial processes today. In 2023, there was an opportunity to explore a project in the areas of Robotics and Automation for a customer. In collaboration with an engineering team from Universal Robots (UR), we (the Strategic Software - Production Integration Team) have prototyped a tailor-made solution for a use case envisioned by the customer. Through this work of integrating UltraFLEX IG-XL with the UR5e program, we were able to able to direct and control the UR cobot from the IG-XL system – automating the processes of picking, placing, testing, and sorting of devices. As you can imagine before, how hand test would go is have an engineer use a pop-sucker to go pick up a chip from a tray, move it to the test head of the tester, secure it in place, then move to the tester desktop to hit run to start testing. And once it is done, the engineer would have to go to the test head, disengage the lid, use the pop-sucker to pick up the chip and bring it over to an output tray. But now with this solution prototyped, everything is handled by the UltraFLEX tester and the UR. From input tray to a pre-aligner, to the test head. And once testing is done, the robot will pick up the chip from the test head and send it to the designated output tray based on bin results. The aim of this paper is to introduce the work of the integration effort and spread knowledge about it in hopes that this would serve as a springboard to other integrative applications between Teradyne products in the future and potentially create new businesses to offer customer efficiency through automation between Teradyne's products.
Accelerating AI Innovation through Strategic Academic-Industry Collaboration
Original Author: Jin Yu
Jin Yu is the head of machine learning for semiconductor test division at Teradyne, where Jin is responsible for leading machine learning initiatives to enhance testing processes, product performance, and internal productivity. In the meanwhile Jin is also a part-time faculty at Khoury College of Computer Sciences, Northeastern University. Prior to Teradyne, Jin was the director of machine learning at Sigify/Philips Research. Jin holds a PhD degree in Electrical and Computer Engineering from Stevens Institute of Technology.
Co-Author: Andy Kittross, Ingo Wahl, Katie Monroe & Scott Diniz
Andy Kittross is a Software Architect focusing on generative AI applications. Prior to this focus, he worked on many IG-XL features, especially DSP. He holds a master's degree in computer engineering from Boston University and a bachelor's in Electrical Engineering from Trinity College, Hartford, CT.
Ingo Wahl is a senior factory applications engineer for the precision power analog group at Teradyne, where he is responsible for defining requirements and solutions for new products on Teradyne test platforms. Prior to Teradyne, Ingo was a test engineer at Infineon Technologies. He holds a Master of Science in electrical engineering from the Karlsruhe Institute of Technology.
Katie Monroe is a Machine Learning Engineer for the AI Team at Teradyne, where she is responsible for developing machine learning models and data science algorithms. She holds a Master of Science in Statistics from the University of Virginia.
Scott Diniz is an engineering director within the semiconductor test division at Teradyne, where he is responsible for AI initiatives and other strategic customer work. He has been at Teradyne for 10 years. Scott holds degrees from UMass Lowell including Bachelor of Science in Electrical Engineering, Masters of Science in Computer Engineering, and Masters of Business Administration.
The advancement of Artificial Intelligence (AI) technologies demands a collaborative approach that leverages the strengths of both academia and industry. Strategic partnerships between leading technology firms and prominent academic institutions have proven essential in pushing the boundaries of AI research, adoption, and ethical implementation. Examples from industry giants such as Meta, Google, etc. highlight the substantial benefits and unique importance of these collaborations. Meta collaborates with Stanford on AI ethics, natural language processing and pioneering responsible AI technologies, while Google partners with UC Berkeley to optimize machine learning algorithms and develop scalable AI solutions. For example, Stanford's Human-Centered AI (HAI) initiative has been key in incorporating ethical design and human-centered thinking into AI development, ensuring technologies are responsibly developed and aligned with human values. These collaborations combine academic research's theoretical depth with industry's practical applications, accelerating AI innovation and ensuring real-world applicability, scalable solution, and ethical considerations. Our collaboration with Northeastern University specifically moves forward the frontiers of AI innovation in semiconductor testing areas like Device Interface Board (DIB) design optimization, explainable AI for robust testing, and AI agents for software/test engineering. Using DIB design as an example, we will develop a domain-specific compilation flow for testing resource allocation. This will analytically express the constraints of instrument and channel assignment. We will create training datasets and use reinforcement learning to optimize the resource allocation for the initial Big Analog device under test. Preliminary results and productivity improvements with the AI-driven optimization flow will be demonstrated.
Creating Your First DSSC Parking Loop: Step-by-Step Instructions
Original Author: Andy Westall
Andy Westall is an FAE for NW SEG at Teradyne, where he is responsible for ETS-800, 88 and 364 product support. Prior to Teradyne, Andy was a Test Engineer at Texas Instruments (legacy National Semiconductor). He holds a BSEE with a minor in Physics from the University of Washington in Seattle.
Co-Author: Thomas Pham
Thomas Pham is a field application engineer for the Solutions Engineering Group at Teradyne, where he is responsible for creating test hardware and software for production testing. Prior to Teradyne, Thomas was a test engineer at Texas Instruments. He holds a Master of Science in electrical engineering from Santa Clara University.
Although there are a several TUG papers about the DSSC on the ETS-800 and a few that use and/or analyze parking loops, there is no Step-by-Step paper on how to make a parking loop from scratch. The result of this lack of training is that I have seen several test programs for large, 90+ pin chips which are paying upwards of several seconds of test time. In this presentation we will cover the following topics: First, we will introduce all aspects of the DSSC coding that need to be placed in the .cpp file. Then, we will introduce all aspects of the various instructions and lines in the eDST vector file. Next, we will show how to implement a DSSC parking loop for both an I2C and a SPI. Lastly, we will review the test time benefits for both protocols as compared with vec write commands. We will explain the differences between the START, STOP, CONTINUE and START_AND_STOP engines. Then we will look at how to set up a user created functions to correctly parse address, data and R/W information. Next, in the section concerning the necessary components of the eDST file, we will look specifically at how to set up the pattern and waveform sheets. Then, we will discuss how to implement the parking loop properly using the C1 and C2 cpp flags. Finally, in the last two sections, two parking loop examples (one for I2C and one for SPI) will be considered. While reviewing these examples the test time improvements of the DSSC will be highlighted. In addition to providing step-by-step instructions for creating your first parking loop, this paper will also provide optimized working code for both I2C and SPI DSSC parking loops. Many customers should be able to leverage these coding examples directly for their needs depending on the specifics of how their chips implement these protocols.
Weaving the RUG: A Structured, Test Specification Driven Process to Create ETS-800 DIB Concept Block Diagrams
Original Author: Ingo Wahl
Ingo Wahl is a senior factory applications engineer for the precision power analog group at Teradyne, where he is responsible for defining requirements and solutions for new products on Teradyne test platforms. Prior to Teradyne, Ingo was a test engineer at Infineon Technologies. He holds a Master of Science in electrical engineering from the Karlsruhe Institute of Technology.
On any tester platform, most production test programs require resource sharing for the best cost-of-test. To improve test economics, a higher site count is desired, which demands more instruments in the test head, unless resource sharing is applied to better utilize the existing configuration. However, thorough resource utilization planning is mandatory to avoid making mistakes when developing the test concept block diagram. With medium to high pin count devices, this can become a tedious and time-consuming task, especially when using many sharing elements like multiplexers, matrices and relays. To keep the overview about which resource is required on which device pin at what point in time, a bulletproof method is required to identify the sharing opportunities while preventing resource conflicts. This presentation outlines a simple step-by-step process starting from test specification to an optimized solution using a table called Resource Utilization Grid (a.k.a. the RUG) to balance resource usage and instrument sharing along the test flow to achieve highest site counts on the ETS-800 utilizing its innovative APEx architecture.
Lessons Learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub
Original Author: James Hannah
James Hannah is the Field Application Engineer for SEG at Teradyne, where he is responsible for supporting customers and teaching classes at the Chandler Training Center. Prior to Teradyne, James has served as an RF Test Engineer for companies such as AT&T, Texas Instruments, and IBM. In addition to these global enterprises, James has also served in key roles in various startup ventures, and he has run his own consulting firm. James holds Bachelor of Industrial Technology from Southern Illinois University and a Bachelor of Professional Management with a Specialty in Business from Nova Southeastern University.
Until recently, the UltraFLEX family of ATE consisted of one platform and one programming language. With the introduction of the UltraFLEXplus, measurements and measurement library code should ideally support multiple platforms. In addition, coincident with the rollout of another platform, the addition of .NET programming introduces two more programming languages, thereby creating a 2x3 matrix of use cases for ATE Test Engineers to learn and support. This matrix imposes a requirement for modular test program development. Further, when these technologies are coupled with a change to a Distributed Version Control System (Git) as well as Productivity Tools (Oasis), a new workflow is needed to support daily test development activities. This paper shares lessons learned while integrating Oasis, Igxl, Visual Studio, Git, and GitHub into a productive workflow for test program development.
Anatomy of a C# Test Method
Original Author: James Hannah
James Hannah is the Field Application Engineer for SEG at Teradyne, where he is responsible for supporting customers and teaching classes at the Chandler Training Center. Prior to Teradyne, James has served as an RF Test Engineer for companies such as AT&T, Texas Instruments, and IBM. In addition to these global enterprises, James has also served in key roles in various startup ventures, and he has run his own consulting firm. James holds Bachelor of Industrial Technology from Southern Illinois University and a Bachelor of Professional Management with a Specialty in Business from Nova Southeastern University.
While transitioning to writing IG-XL test programs in .NET, specifically in C#, the move from procedural programming to object-oriented programming is taking place. A major part of this transition is consideration of this question, “What is a Test Method?” This paper dissects the traditional monolithic test method and transforms it into a composition of smaller methods. There exists multiple drivers for this architectural transition. The first of which is to leverage object-oriented programming techniques made available in .NET and C#. Next, the need for fully vetted reuse libraries is driving more generic solutions, as well as Unit Testing. However, not every piece of the test method content should be part of the reuse library. Instead, some pieces should exist in the device-level code so that is can be customized by each team and even each Product Engineer. So, we will consider the components of a test method and access what content needs to be library code and what content needs to be carved out of the library, effectively splitting the traditional test method into smaller parts that don’t all live in the same place. This architectural shift optimizes both reuse and flexibility.
Efficient Awg Pattern creation using SupportCodes MFLApp RampsLoader
Original Author: Shu-Wei Ting
Shu-Wei, TING is the Technologist for Eagle Test Systems Applications at Teradyne, where he is responsible for test developments and applications on Eagle Test Systems testers. Prior to this role, he was the Applications Engineer at Eagle Test Systems. He holds a degree in Electrical and Electronic Engineering from Curtin University of Technology, Western Australia.
This paper introduces a convenient, code-based option for loading Arbitrary Waveform Generator (AWG) patterns using the SupportCodes MFLApp RampsLoader. Traditionally, the ATE (Automated Test Equipment) AWG Pattern Editor has been the standard tool for creating AWGs. However, when more than 10 AWGs are required for a test application, the default ATE AWG Pattern Editor becomes cumbersome, tedious, and slow, complicating the preparation process. Collaborative efforts among multiple engineers often lead to AWG file conflicts, resulting in file corruption and significant time loss due to recompilation, even for minor changes. Frequent addition and modification of AWGs are integral to the development and debugging process. This presentation will detail the use of the SupportCodes MFLApp RampsLoader, including code examples to create 16x Battery Management System (BMS) cell voltages with AWGs and actual scope captures. The potential applications for the SupportCodes MFLApp RampsLoader are vast and limited only by one’s imagination. Additionally, the implementation of SupportCodes MFLApp RampsLoader enhances workflow efficiency by providing a streamlined and automated method for AWG pattern creation and management. This not only reduces the likelihood of human error but also significantly cuts down on development time. The capability to seamlessly integrate this loader into existing testing frameworks ensures minimal disruption while maximizing productivity. By leveraging this tool, engineering teams can focus more on innovative problem-solving and less on the mechanical aspects of AWG pattern generation.
MyInfo Copilot: Elevating Information Retrieval
Original Author: Nathan McCrory
Nathan McCrory is a Factory Applications Manager based in Plano, TX. He graduated from Texas A&M University in 2007; started working at Teradyne as a Field Applications Engineer supporting Texas Instruments; developed test solutions for a variety of products in the MCU, BMS, automotive, and computing space; and actively participates in AI and productivity tool development to improve our user's experience, efficiency, and capability.
Co-Author: Andy Kittross
Andy Kittross is a Software Architect focusing on generative AI applications. Prior to this focus, he worked on many IG-XL features, especially DSP. He holds a master's degree in computer engineering from Boston University and a bachelor's in Electrical Engineering from Trinity College, Hartford, CT.
MyInfo Copilot aims to elevate how test engineers interact with key pieces of information to improve their efficiency with Teradyne products. This presentation is to provide users with a snapshot of the existing capability, recap the methodology used for providing the LLM with contextually relevant information, discuss ways that Teradyne has prioritized IP protection, review how quality is optimized, and cover the benefits for why each of these design decisions were chosen. As of today, MyInfo Copilot comprehends information about UltraFLEXplus, UltraFLEX, ETS-800, and ETS-88 Family of test platforms, it’s capable of providing users with productivity tool identification when applicable, and able to reference TUGx presentations and test techniques to provide users with feedback from user-based expertise.
Setup, Implementation, and Benefits of the RCM (Remote Connectivity Matrix)
Original Author: Daniel Gray
Daniel Gray is a Field Applications Engineer supporting Eagle platforms at Teradyne, where he is responsible for providing applications support on new and existing solutions. Prior to this role, Daniel has experience as a Factory Applications Engineer and Field Product Specialist at Teradyne. He holds a Bachelor of Science in Electrical Engineering from the University of New Hampshire.
As time goes on, the complexity of devices continues to increase, while engineering teams are pressured to develop test solutions as fast as possible. Teradyne developed the Remote Connectivity Matrix (RCM) to support test engineering teams meet these demands by reducing time to market. When scattered geographic locations can limit the productivity of test engineering resources, having a way to increase the amount of productive remote debugging is essential to meet the needs of an evolving global industry. The RCM enables global teams to increase their productivity, and when used in concert with other tools, can reduce the effort needed to arrive at a quality test solution. While the ETS-800 already provides four sectors’ worth of debugging potential by separating a single engineering tester into four independent debugging stations, adding the RCM and oscilloscopes (and appropriate DIB design) to this setup can aid geographically diverse teams in developing a test solution fast and reliably, by eliminating most of the need for manual probing. This paper demonstrates the implementation and benefits of using the RCM in an engineering environment in a recent test development project.
IG-Correlate and STDFStats Toolset Feature Updates
Original Author: Daniel Benjamin
Daniel Benjamin is the factory applications lead for IG-Correlate at Teradyne, where he is responsible for maintaining and coordinating improvements for the IG-Correlate Toolset. Prior to this role, Daniel was a test development engineering coop at Teradyne. He holds a bachelor's degree in computer engineering from University of Massachusetts Lowell.
Co-Author: Zoe Gui & Tracy Jia
Zoe Gui is the factory applications engineer at Teradyne, where she is responsible for software development for J750, UltraFlex and UltraFLEXplus tester. She holds a bachelor's degree in computer science and technology from Anhui Jianzhu University.
Tracy Jia is the factory application engineer for software developing at Teradyne, where she is responsible for developing various software tools for UltraFLEX or Eagle testers. She holds a Bachelor of Engineering in software engineering from Xidian University.
In 2024, IG-Correlate was introduced as a tool that can be used to provide insight into pre-correlation data. User feedback has driven enhancements in data readability, visibility, accessibility, and support for additional pre-correlation analysis use cases, as well as performance improvements. These updates have shifted IG-Correlate to better align with user expertise and usability expectations. Such can be seen in core features like the Readiness History Comparison, the Quick Stats panel, and the Measured Data plots, where the accessibility and representation of data has been adjusted and improved. New functionality such as Multiple Datasets and Target Sets give the user more control over the assessment of their data. Since it's introduction, IG-Correlate has continued to improve the Test Engineering pre-correlation experience by enabling users to focus on and evaluate key problem areas. Through the simplification of that assessment process, Test Engineers can more efficiently investigate, improve, and resolve unstable tests.
Support Multiple Test Platforms via Tester Abstraction Layers
Original Author: Scott Bielski
Scott Bielski is a software engineer on the PortBridge team at Teradyne, where he is responsible for strategic design in solutions. Prior to this role, Scott worked on the DC software team at Teradyne. He holds a bachelor's degree in computer and electrical engineering from Northeastern University.
Co-Author: Richard Fanning
Richard Fanning is the software architect for the PortBridge project at Teradyne, where he is responsible for developing the software, marketing the product and determining the product roadmap. Prior to working on PortBridge, he worked on numerous products for the FLEX, UltraFLEX and UltraFLEXplus platforms. He holds a degree in Computer Science from Harvey Mudd College.
The Tester Abstraction Layer (TAL) is a novel approach to ATE test design that provides a platform-agnostic and extensible Application Programming Interface (API) in order to simplify test development. TAL is designed to abstract away the complexities and idiosyncrasies of individual testing platforms and provide a unified, easy-to-use API for test development. This abstraction layer allows test program developers to write tests once and run them on multiple platforms without any modifications. TAL acts as a bridge between test program logic and the underlying testing platforms, encapsulating differences between the platforms and translating generic test commands into platform-specific instructions. TAL additionally allows for test portability. Since TAL provides a platform-agnostic API, tests written for one platform can be easily ported to another platform. This can be particularly useful with multi-tiered test strategies, where common test logic needs to be executed on multiple platforms, such as ATE and SLT, to ensure test completeness. This document will describe the design principles, benefits, and applications of TAL, namely siting the Tester API project.
DesignLink: Streamling Test Pattern Deployment with Automated Solutions
Original Author: Richard Fanning
Richard Fanning is the software architect for the PortBridge project at Teradyne, where he is responsible for developing the software, marketing the product and determining the product roadmap. Prior to working on PortBridge, he worked on numerous products for the FLEX, UltraFLEX and UltraFLEXplus platforms. He holds a degree in Computer Science from Harvey Mudd College.
Design engineers generate test patterns that are typically handed off to test engineers to be incorporated into an integrated test program. As test program size, chip complexity and the number of patterns needed for complete coverage grows, the cost when these newly introduced patterns fail increases exponentially. This leads to lengthy iterations between designers and test engineers. DesignLink provides a web-portal that allows design engineers to submit patterns for testing into an automated, out of the box solution, that will compile, test and gather full execution results. This provides the test engineering team with confidence in the pattern while also tracking a full status of all the patterns for a particular device which gives team leaders a general overview of the bring up status.
ScanFalcon: A Custom Data Consumer for IG-XL
Original Author: Jens Nagel
Jens Nagel is part of the Factory Applications Group at Teradyne. In the last 8 years, he has been supporting IG-XL based platforms in various applications for the Automotive segment, as well as MST based conversions for the hybrid instrument generation. As time went on, he focused on the development of software tools for test program generation and productivity improvements. Currently, Jens is working on GUI based debug features for the Eagle Test Platform.
In semiconductor testing, accurate and efficient logging of results is crucial. IG-XL offers integrated mechanisms to log results into Standard Test Data Format (STDF) files, ASCII datalogs, or display them in an output window for immediate verification. While these built-in options cater to many standard needs, certain applications require specialized logging solutions tailored to specific customer requirements. To address these needs, IG-XL supports the attachment of custom data consumers.
This presentation will delve into the general interface provided by IG-XL for custom data consumers and introduce ScanFalcon, an existing custom data consumer uniquely designed for ScanFailProcessing. ScanFalcon enhances the flexibility of data logging by allowing users to define the output log file using a format definition file and adjust settings through a configuration file. We will explore the key features and benefits of using ScanFalcon, including its adaptability to various logging requirements and its ability to streamline the data verification process. Attendees will gain insights into the implementation and configuration of ScanFalcon, demonstrating how it can be utilized to optimize semiconductor testing workflows.
The Power of the .NET Ecosystem
Original Author: Dan Thornton
Dan Thornton is the lead apps engineer for the .NET Development in IG-XL project. He was lured back into applications (from software engineering) to participate in this important project. In Dan's words, "Great Scott! We're going back to the future!"
The .NET Development in IG-XL feature adds two new programming languages to a Test Engineer's arsenal: VB.NET and C#. But .NET is so much more than its languages -- .NET is an entire ecosystem. I will demonstrate how the multiple facets of the .NET ecosystem can improve a Test Engineer's efficiency, from C# inside Visual Studio, through Oasis, DevOps and your own personal toolkit developed in PowerShell or .NET.