Abstracts

For some chips, especially large and complex devices such as HPC, AI, and ADAS, if only a portion of the cores fail, the device is classified as Partial Good, meaning it is still considered usable. In ATE testing, it is necessary to categorize Partial Good devices based on which cores have failed. As chips become more complex and additional test insertions are introduced, including CP, FT, and tri-temperature, determining Partial Good status becomes increasingly challenging. This presentation uses an example of an AI device to demonstrate how to handle Partial Good cases when multiple insertions are involved. It also introduces suggested code approaches to make the process easier and more efficient. In our development, we created three different code modules, each using a distinct method to determine Partial Good status. The modules include SSN patterns, MBIST patterns, and IP tests. This presentation explains the Partial Good logic for each module and outlines best practices. Finally, we describe how to add a data logging format to support analysis of Partial Good status.

Serial Peripheral Interface, or SPI, is a widely used communication protocol for high-speed serial data transfer. Quad SPI enhances traditional SPI by using four data lines during the command, address, and data phases, enabling wider data transfers and significantly increasing throughput. These advanced protocols introduce new considerations for Automatic Test Equipment, especially in managing timing accuracy, vector complexity, and flexible debug capabilities across a wide range of device applications. UltraFLEXplus systems play an important role in bridging design and test workflows to address these challenges. This presentation provides an overview of SPI and Quad SPI technologies from both design and test perspectives. It includes key configuration and integration steps such as driver installation, Port Bridge sheet creation, pin group definition, and XML protocol file loading. The structure and purpose of XML protocol definition files are also discussed, along with how the Protocol Definition Editor validates command formats and protocol frames. Debug methodologies using Protocol Studio are demonstrated, including techniques for monitoring transactions, analyzing protocol behavior, and verifying data integrity to ensure accurate and efficient test execution. A real project implementation is presented to illustrate how UltraFLEX and UltraFLEXplus Port Bridge functionality and integrated debug features can reduce test time and improve development efficiency in production environments.

Testing image sensor devices requires analyzing captured image data at the pixel level to determine pass or fail results. As pixel counts in image sensors continue to increase significantly, this analysis demands substantially more computing power. For example, a few years ago, mobile devices typically featured sensors with 8 to 12 megapixels, while today’s smartphones often exceed 50 megapixels, with even higher resolutions expected in the near future. As a result, image analysis time scales directly with pixel count, and conventional CPU-based solutions can lead to test times increasing by a factor of four or more. To address this challenge, a heterogeneous computing approach is introduced that leverages both CPU and GPU resources to significantly reduce test time. This presentation highlights the performance benefits of this approach on UltraFLEXplus and IP750ExHD platforms, evaluating both test time improvements and cost impact. This presentation also discusses key implementation challenges along with the solutions developed to overcome them.

Modern microcontrollers and processors continue to implement new design-for-test methodologies to reduce the amount of data that must be analyzed outside of the device under test. However, for failure analysis, there is an increasing need to read back larger amounts of data from the device, even in production environments. Newer testers with larger capture memories and faster data transfer interfaces, such as UltraFLEXplus, support a range of capture solutions for different use cases. These systems can efficiently capture various types of data, from simple register contents to large volumes of scan output, as well as raw mixed-signal data from an ADC. In many cases, device data is transmitted through a serial interface pin, which may require serial-to-parallel conversion before analysis can begin. This presentation provides an overview of the different capture memory options, including CMEM, HRAM, and DSSC on UltraFLEXplus. It describes the hardware differences and compares the efficiency of each capture memory across a variety of use cases for single pin readback. It also includes sample code demonstrating how to implement these solutions in the .NET environment of IG-XL. Finally, it offers guidance on selecting the most appropriate capture memory for specific use cases.

This presentation extends prior work on UltraPort-PCIe by examining scan testing over high-speed interfaces, specifically PCIe. It begins with a comparison of GPIO-based scan and HSIO scan, highlighting improvements enabled by PCIe IP, DMA engines, and AXI bus architectures. UltraPort features used for advanced scan testing are then explored, including optical links, expanded memory resources, and fail processing capabilities. These features support high-volume pattern execution and enable more efficient mismatch triage. Proof of functionality is presented using a high level workflow for SCAN over PCIe and HSIO pattern generation process. New tools are also discussed, such as the HSAT pattern debug Tool and support for modern file formats like .patsx, which simplify pattern visualization and modification across platforms. The discussion continues with presenting FPGA-based DUT proxies developed with customers, demonstrating scalability, performance, and practical deployment considerations for HSIO-based scan in advanced device test environments. Finally, factors to be considered for DMA engines will be presented, showcasing scenarios that enable optimal performance and enhanced flexibility.

Mission-mode testing on UltraPort PCIe enables execution of real application-level workloads directly on Automated Test Equipment, allowing validation of end-use functionality rather than relying solely on structural or pattern-based tests. Traditional ATE approaches are limited in their ability to replicate full system behavior, creating a disconnect between bench validation, production test, and system-level testing environments. This presentation introduces a methodology that bridges this gap by leveraging PCIe as a high-speed communication interface to control the device under test and deliver workload-driven testing within the ATE environment. By enabling real-time interaction with the device using system-relevant traffic, the approach provides deeper visibility into functional performance and system behavior. The solution supports reuse of existing development and validation workflows, reducing effort required to transition from bench testing to production environments. It also improves correlation across different test stages, ensuring more consistent results and faster issue identification. A practical implementation example demonstrates how mission-mode testing can be applied to complex devices, highlighting improvements in workflow efficiency and validation consistency. Overall, this approach enhances test coverage, reduces development complexity, and accelerates the path from silicon validation to high-volume production, while requiring careful consideration of interface performance and device-specific constraints.

High-definition and high-refresh-rate display requirements have become standard in modern mobile devices, automotive displays, and embedded systems. MIPI has developed a series of serial communication interface standards for mobile and embedded applications, designed to reduce pin count, lower power consumption, and improve performance. DSI D-PHY is a high-speed serial interface protocol for display modules defined by the MIPI Alliance and operates on the D-PHY physical layer. PRBS testing is a physical layer validation method used to evaluate signal integrity, particularly for the differential data channels in high-speed mode. This presentation introduces a testing method on the UltraFLEX platform for synchronizing the clock phase of DSI D-PHY and capturing the PRBS data stream, demonstrating how this approach supports reliable validation of high-speed display interfaces.

This presentation explores the application of the Tessent Stream Scanning Network, or SSN, with a focus on implementing tester-compare on the UltraFLEXplus platform. It outlines the test flow for tester-compare, including how to identify failing cores, interpret mapping data, and use IG-XL embedded functions to process failure results. Based on prior project experience, the discussion also covers the use of the Test Insight tool to convert STIL files into IG-XL ATP files, along with common debugging challenges encountered during SSN testing. These issues are not limited to SSN, but are relevant to general ATPG workflows. In addition, it explains the need to adjust SSN I/O timing and provides an overview of methods such as rough search, I/O timing optimization, and linear fitting after collecting the required data. Finally, it describes the fail logging approach used for SSN, including both text and STDF record formats, and compares their performance.

This presentation introduces a temperature-calibration solution for ADAS products using built-in thermal transistors. Accurate test temperature is a critical parameter for automotive devices throughout ATE testing, as defined by standards such as AEC-Q100, which specifies reference temperatures for qualifying automotive-grade ICs. However, due to physical constraints in wafer testing, high-accuracy temperature measurement in CP environments remains challenging. To address this issue, the proposed method combines an on-chip transistor with a load-board temperature sensor to achieve more precise thermal monitoring. Under fixed test conditions, this method enables characterization of temperature variation across individual dies, improving measurement accuracy and contributing to higher production yield.

This presentation addresses the long-standing challenge of implementing efficient, accurate on-chip IR (voltage drop) monitoring for large-scale SoC testing and verification. Traditional approaches often rely on on-chip Analog-to-Digital Converters (ADCs) to digitize analog signals for IR monitoring, but these methods can introduce significant area overhead and increased software processing complexity. The proposed solution uses an innovative Digital Voltage Sensor (DVSG) that replaces conventional ADC-based monitoring with a digital-circuit implementation, enabling faster on-chip IR detection and response while remaining well suited for high-volume production. The ATE test methodology establishes a closed-loop flow that spans IR characterization, data processing, and DVSG-based IR monitoring. Multiple sensors are distributed across different power domains during device design. DVSG monitors IR behavior by configuring path delay through adjustments to the data path, launch clock path, and capture clock path. When abnormal behavior is detected, a Compare Fail (CFAIL) flag is asserted. During characterization, the ATE sweeps power-domain voltages and delay configurations, records CFAIL results, and identifies warning thresholds by locating adjacent voltages that produce different outcomes under the same configuration. The corresponding configuration “gear” selections and warning voltages are then captured. Repeating this process across conditions yields an optimized set of gear configurations and threshold voltages, which are used to generate production-ready ATE patterns for IR monitoring. During monitoring, the test patterns initiate representative processor workloads and read back CFAIL results to enable precise evaluation of IR impact. Consistency checks against large system testing are also used to validate accuracy and practical effectiveness. Verification results show that the DVSG-based ATE solution achieves 5 mV IR monitoring accuracy while reducing software processing complexity and improving test efficiency. In addition, because the digital IP area is approximately one-fiftieth of a comparable analog implementation, more sensors can be integrated within the same area, providing stronger coverage to support high-performance, low-power SoC designs.

Zero Defect, or ZD, is no longer simply a goal but a contractual requirement for automotive devices under AEC-Q100. With the increasing adoption of L2+ and L3 autonomous driving, ADAS devices must shift ZD screening tests, such as High Voltage Stress Test and Memory Data Retention, to wafer-level Chip-Probe testing to reduce downstream fallout to parts-per-million levels. ADAS devices now feature thousands of pins, higher power consumption, increased current demand, multi-core architectures, and multiple grade binning requirements. These factors make ZD screening at the Chip-Probe stage particularly challenging. This presentation introduces key ZD test methods on ATE, with a focus on High Voltage Stress Test, especially Dynamic Voltage Stress, and Memory Data Retention. It details the implementation of these tests on UltraFLEXplus, where Dynamic Voltage Stress operates at very high voltage and high current, while Memory Data Retention testing is performed at lower voltages determined through characterization. The discussion also highlights best practices for protecting probe card needles and managing multiple binning requirements during Memory Data Retention testing, providing guidance for reliable and efficient implementation.

The evolution of semiconductor devices continues to drive significant changes in digital testing methodologies. Increasing vector memory requirements have emerged as a key trend, as next-generation devices demand greater capacity to support expanded test coverage and emerging fault models. While Electronic Design Automation tools continue to introduce techniques to manage memory growth, these solutions primarily slow the trend rather than eliminate it. In both production and characterization workflows, testing typically begins by utilizing the maximum tester resources available before further optimization is applied. New scan requirements are reshaping test architectures, introducing capabilities such as SSN and scan fabric integration, core identification, and decoupling of pin and chain assignments. At the same time, higher data rates are becoming essential to meet performance demands. UP5000-EM significantly increases vector memory capacity compared to UP2200+ and supports data rates up to 5 Gbps for both single-ended and differential signaling. Large digital and AI devices are further driving the need for enhanced flexibility, improved precision, and reduced cost of test. Maintaining compatibility with UP2200+ remains an important requirement to ensure a smooth transition for existing programs. Together, these trends highlight the need for scalable, high-performance solutions to address the growing complexity of digital testing. This presentation provides an overview of the new capabilities of UP5500-EM and how it addresses these evolving requirements in digital test environments.

The rapid growth of AI workloads in hyperscale data centers is driving the need for rigorous validation of ultra-high-speed interconnects aligned with emerging industry standards. UltraPHY224G, a next-generation physical layer ATE instrument for the UltraFLEXplus test system, enables comprehensive characterization of 224G serial links essential for next-generation architectures. It integrates a 120 GBaud BERT transmitter and receiver along with a 70 GHz equivalent-time oscilloscope to support a wide range of measurement needs. The platform supports both NRZ and PAM4 signaling and includes advanced DSP features such as CTLE, FFE, and DFE for precise signal integrity analysis. This presentation highlights the role of UltraPHY224G in compliance and performance verification for key industry standards, including OIF CEI-224G, IEEE 802.3df for 800G Ethernet, and PCIe Gen6. Through selected use cases, it demonstrates how the platform enables validation of link reliability, optimization of error performance, and acceleration of deployment for high-bandwidth interconnects in AI-driven data center environments. UltraPHY224G integrates eight BERT transmit channels, eight BERT receive channels, and eight oscilloscope receive channels, with supported data rates up to 224 Gbps. The transmitter includes multi-tap FFE for precise equalization, while the receiver incorporates DFE, reflection cancellation, and bandwidth extension filters, along with built-in clock data recovery. The integrated oscilloscope enables advanced eye analysis, NRZ jitter decomposition, and PAM4-specific measurements such as relative level margin and dispersion metrics. Supported test patterns include PRBS, stressful patterns, and square waves, enabling compliance testing across multiple standards. These capabilities allow engineers to verify signal integrity, meet BER targets, and validate performance requirements for next-generation high-speed chip-to-chip interfaces.

The DCVS instruments on UltraFLEXplus support programmable slew rate control, a feature now available in IG-XL versions 11.0 for UVS64 and UVS256, and 11.10 for UVS64 HP. This capability can be configured not only in levels sheets but also directly in code using VBT and C#. By controlling the slew rate, users can manage voltage rise and fall times and reduce overshoot and undershoot during supply transitions. This feature is especially useful for applications such as voltage threshold searches on power supply pins, including power-on reset and brownout conditions. It also enables precise control of voltage relationships between DUT supplies, such as maintaining a defined voltage difference between two rails or ensuring one supply remains higher than another throughout power-up and power-down sequences without requiring discrete DC stepping. This presentation explains how to configure slew rate control in both levels sheets and code, highlights potential pitfalls, and provides guidance on how to avoid them. It also includes practical examples with captured waveforms to illustrate key behaviors and best practices.

The UVS64-HP is a high-power DCVS instrument designed for the UltraFLEXplus platform, building on the existing UVS64 architecture while introducing significant enhancements in performance and capability. The instrument maintains the same channel density and channel-merging flexibility as UVS64, while extending its functionality to support more demanding power applications. This presentation provides a detailed overview of the UVS64-HP and its key advancements. It highlights the increased current capability of up to 20 A per channel, compared to 5 A on the previous generation, along with a higher sampling rate of 1.2 Msps for voltage and current measurement and capture. It also introduces a high-speed voltmeter that enables waveform capture at rates up to 125 Msps, allowing for more detailed signal analysis. In addition to improved performance, the UVS64-HP enables simultaneous measurement and capture of voltage and current, as well as concurrent monitoring across multiple sense lines within merged channel groups. It also supports flexible selection of sense lines for regulation feedback, enabling more precise Kelvin-based measurements and control. The instrument introduces an Intelligent Power Interface that provides enhanced system visibility and protection features, including analog current monitoring outputs, digital warning signals, fault inputs for shutdown control, and alert signaling capabilities. These enhancements improve system safety, control, and diagnostic capability in high-power test environments. Overall, the UVS64-HP delivers expanded power handling, improved measurement precision, and advanced system integration features, enabling more efficient and accurate testing of high-current applications on UltraFLEXplus.

Test program development timelines are becoming increasingly compressed, leaving limited time to identify and resolve critical issues. One of the most time-consuming challenges is memory leakage, which can impact system performance and reliability if not addressed effectively. Identifying the root cause requires the right tools, targeted data collection, and a structured investigation process. This presentation demonstrates how to detect, measure, and resolve memory leakage issues through a real-world example. It explains what constitutes a memory leak, outlines methods for accurately measuring memory usage, and presents a systematic approach to identifying root causes. A step-by-step investigation methodology is introduced, leveraging advanced tools such as Quality Monitor, Oasis, and Excel-based scripting to isolate problem areas and validate corrective actions. The discussion focuses on practical strategies that enable engineers to diagnose issues more efficiently, reduce debug time, and implement effective fixes. Overall, the approach provides a repeatable framework for identifying and resolving memory leakage issues, helping teams improve program stability and meet tight development schedules.

UltraPort-PCIe6 builds on the UltraPort-PCIe platform by introducing PCIe Gen6 capability to UltraFLEXplus, enabling both scan over PCIe and mission-mode testing at higher data rates. The instrument is rearchitected using a Non-Slot Instrument design that performs signal retiming close to the device interface, allowing delivery of up to 64 Gbps PAM4 signaling to the DUT while maintaining integrated PPMU functionality. This presentation describes the new architecture and its impact on test performance and design efficiency. The Non-Slot Instrument approach enables at-speed loopback up to PCIe Gen6, improving PHY-level test coverage while simplifying DIB design by eliminating the need for high-speed switching components. A new DIB block design maintains compatibility with existing UltraPort-PCIe interfaces while introducing additional auxiliary signals to better support PCIe Add-In Card compliant devices. The platform also includes an upgraded server architecture with increased system memory and a next-generation PCIe Gen 5 CPU, improving overall performance for demanding test applications. These enhancements support higher throughput, improved scalability, and more efficient handling of complex workloads. Overall, the solution advances high-speed interface testing by delivering greater performance, simplified hardware design, and enhanced flexibility for both scan and mission-mode applications on UltraFLEXplus.

This presentation addresses this user-experience gap by introducing tags on pattern modules and a clean access model in IG-XL with application code library in C#. Tags, including the new module tags and preexisting vector tags, bind design-side metadata to pattern files, eliminating potential metadata mismatch caused by manual pattern editing and making SSN setup/payload/end pattern debugging consistent. Our solution builds on recent IG-XL features for tag management-culminating in a Custom Tags Repository option that lets Test engineers curate and query tags consistently throughout Test Flow-and shows how Test Insight's TDL tool can inject tags. This presentation will demonstrate tangible UX improvements: faster coding, fewer integration defects, clearer diagnostics flow, and smoother debugging experience for SSN patterns.

Delivering reliable, flexible communication between the tester and the Device Under Test is essential for modern ATE workflows. Traditional approaches often require integration within IG-XL, which can add complexity and increase development time. This presentation introduces the Blind Mate Auxiliary Connector, a streamlined solution for delivering USB and Ethernet connectivity directly to the Device Interface Board. It enables efficient communication with the device under test while reducing setup overhead and simplifying system integration. The solution allows engineers to interact with the device using custom code, rather than relying on predefined IG-XL flows. Configuration can be performed through an UltraPort server or a standard laptop, enabling faster setup and greater flexibility during development and debugging. For devices that require serial protocols such as I²C or SPI, the approach uses widely available USB-to-serial converters, providing a cost-effective and easily deployable interface. This makes it possible to support a broad range of communication requirements without specialized hardware. Overall, the Blind Mate Auxiliary Connector accelerates development workflows by simplifying connectivity, increasing flexibility, and maintaining reliable communication performance across a wide range of applications.

Electrical Failure Analysis (EFA) is a critical tool used in the identification of defects which can cause broken scan chains or clock paths in a Device Under Test (DUT). Traditionally, EFA relies on Automated Test Equipment (ATE) combined with electrical fault isolation (EFI) techniques like Laser Voltage Imaging (LVI) and Probing (LVP), collectively referred to as LVX. This methodology is dependent on the ability of the ATE to generate infinite loops and test pattern predictability for observation. The Siemens Streaming Scan Network (SSN) provides advanced capabilities in pattern generation. While an additional layer of complexity is added, this new Design for Test (DFT) architecture provides features designed to support these EFA requirements. This presentation will detail the application of LVX techniques utilizing the SSN architecture. We will demonstrate this implementation on a real device using the Teradyne UltraFlex test platform. This work is a collaborative effort between Siemens EDA, Nvidia NBU Israel and Teradyne, showcasing a robust solution for complex failure analysis challenges.

Profiling and analyzing device power consumption is becoming increasingly critical as next-generation AI compute devices demand higher power levels and tighter operating margins. Accurately understanding where and how power is consumed is essential to prevent device damage, optimize performance, and ensure reliable operation during test. This presentation introduces enhanced power profiling and analysis capabilities enabled by the UVS64-HP instrument and the Power Management tool suite. The UVS64-HP provides advanced measurement features, including simultaneous voltage and current capture, high-speed waveform acquisition, and event-driven data collection, along with flexible sensing configurations and an intelligent power interface for real-time monitoring and feedback. Leveraging these capabilities, the Power Management tool suite enables comprehensive power profiling across an entire test program without requiring modifications to existing test code. Engineers can easily define configurable profiling setups with minimal code changes, specifying where and how power measurements are captured during execution. Both deterministic low-speed profiling and event-triggered high-speed profiling can be combined to focus analysis on critical conditions. To manage large datasets, the solution includes automated data processing that reduces dataset size while preserving key characteristics for analysis and visualization. The Power Analysis tool allows engineers to explore results interactively, providing both graphical and tabular views, along with contextual information such as test flow stages, system events, and measurement conditions. Custom calculations and comparisons can also be applied to further analyze device behavior over time. Overall, this approach provides a powerful and scalable framework for understanding device power consumption, enabling improved visibility, faster debug, and more informed decision-making when testing complex, high-power AI devices.

This presentation showcases a significant engineering transformation that enables advanced FPGA and AI accelerator testing to run on UltraFLEXplus using the IG-XL .NET environment. As one of the first FPGA device implementations on this platform, it establishes a new baseline for adopting next-generation test software architectures within manufacturing workflows, delivering improved coverage, enhanced debug capability, and faster ramp readiness for future device families. Driven by scalability limitations in legacy test platforms, the solution adopts a modern UltraFLEXplus architecture featuring site-synchronous timing, advanced DPS resources, and high pin count instrumentation, with support for multi-site testing from two up to eight sites. The approach includes a redesigned test program architecture in IG-XL .NET, along with pattern and timing reconstruction using Test Program Generator, Test Class Library, and Pattern Generator tools. Modular test classes are implemented to improve maintainability and scalability across multiple product generations. Key technical challenges are addressed, including managing electrical and thermal balance in multi-site DIB layouts, optimizing socket symmetry, and achieving full functional and parametric correlation across temperature conditions. Additional effort is focused on aligning legacy pattern behavior with the UltraFLEXplus execution model and restructuring test programs to support high-parallelism environments. The implementation also integrates with existing data formats and infrastructure, including production data flows and security frameworks, while applying parallel test efficiency techniques to maximize multi-site scalability. The results demonstrate a scalable manufacturing solution that enables up to eight-site parallel testing, improves debug efficiency, reduces tester overhead, and provides a reusable IG-XL .NET framework to support future FPGA and AI accelerator devices in high-volume production.

The ETS-800 platform provides advanced multiplexing capabilities through MCMux and SPMB instruments, enabling high-voltage switching, increased site counts, and reduced reliance on DIB-based relay solutions. These instruments support both static configurations and dynamic, pattern-based operations, allowing engineers to modify multiplexing states during pattern execution for applications such as RDSON measurement, multi-node sensing, and other complex switching scenarios. This presentation introduces a software library designed to automate the generation of MCMux and SPMB patterns, addressing the complexity of manual pattern creation. Traditionally, engineers must encode pattern steps, construct 32-bit data words, and verify binary-to-hex conversions, resulting in a time-consuming and error-prone process. The proposed solution allows users to define desired multiplexing states at a higher level, with the library automatically handling pattern construction and formatting. The tool also includes built-in validation features, providing visual feedback to help ensure correct pattern behavior and reduce debugging effort. By abstracting low-level pattern implementation details, the solution improves development efficiency and reduces the likelihood of errors during pattern creation. In addition, the development of this library demonstrates how modern software techniques, including AI-assisted workflows, can accelerate the creation of engineering tools and improve productivity. The presentation also explores the advantages and limitations of pattern-based multiplexing, including its potential to reduce overall test time compared to static approaches. Considerations for applying pattern-based methods across different instruments and test scenarios are discussed. Overall, this solution simplifies pattern generation, reduces manual effort, and enables faster development cycles, providing a more efficient and scalable approach to implementing dynamic multiplexing in ETS-800 test environments.

Large Language Models (LLMs) have evolved from conversational assistants into agentic systems that can plan and execute multi-step engineering tasks. Applying general-purpose AI to specialized ATE development, however, often fails without deep domain context and enforceable workflow rules. This presentation introduces a practical approach that extends AI agent capability using dynamically loadable “Skills” that package domain expertise, standardized workflows, and execution constraints into reusable modules. The approach enables ATE engineers to apply AI effectively without requiring extensive programming or prompt engineering. Example Skills include a cross-platform test program conversion Skill that performs guided script execution to translate programs into the IG-XL environment, a C# reference-architecture test method generator that combines Retrieval-Augmented Generation (RAG) with template-based generation, and a VBT code-checking Skill that enforces naming conventions and coding standards using natural-language rules captured from internal best practices. Results show that pairing general-purpose AI with domain-specific Skills can reduce development time while maintaining output quality and supporting enterprise IP protection expectations. The framework also creates a repeatable mechanism for expert-to-AI knowledge transfer, with potential future extensions in areas such as automated pattern compilation and DIB definition automation.

Transparent multi-site data handling has long been a hallmark of IG-XL. With SiteGenerics, we take this capability to the next level - introducing a streamlined use model and powerful new features enabled by the recent integration of .NET development within IG-XL. By overcoming limitations inherent to the VBA environment, SiteGenerics deliver a consistent and efficient approach to data processing across sites, pins and samples. This presentation will cover the design concept of SiteGenerics, demonstrate their advantages through practical examples, and review the current feature set. We’ll also share an outlook on enhancements delivered in upcoming IG-XL releases. Finally, we’ll show how leveraging .NET simplifies the creation of feature extensions for IG-XL - demonstrated through the first fully functional SiteGenerics implementation. Whether for rapid prototyping or extending IG-XL test code, .NET empowers users to seamlessly add custom capabilities and accelerate innovation.

In integrated circuit manufacturing, evaluating measurement system capability is essential to ensure data accuracy and process control. Gage studies, particularly Gage Repeatability and Reproducibility, are widely used to assess the variability introduced by measurement equipment and operators, helping quantify overall measurement precision and potential bias. This presentation describes a structured approach to performing Gage R&R analysis using the Exensio platform, a widely used correlation and analytics tool. While several commercial solutions exist for this purpose, the focus here is on leveraging Exensio to execute statistically robust studies within an existing data analysis environment. The methodology outlines a complete workflow for conducting Gage studies, including data collection, preparation, and formatting to ensure compatibility with the platform. Emphasis is placed on best practices for acquiring consistent and well-structured datasets, enabling accurate and reliable analysis. The discussion also explores the different analytical methods supported by the platform, including variance-based approaches and correlation-driven techniques. These methods provide engineers with deeper insight into measurement system performance, helping identify sources of variation and opportunities for improvement. Overall, this approach enables efficient evaluation of measurement capability within a unified analytics framework, improving data quality, strengthening process confidence, and supporting more informed decision-making in semiconductor manufacturing.

As semiconductor test programs become increasingly complex, development teams face growing pressure to deliver high-quality solutions within compressed timelines. Code reuse through shared TestCode libraries has become a critical strategy for accelerating development and ensuring consistent functionality across multiple device programs. However, the quality and reliability of these libraries have a direct impact on overall test performance and yield. This presentation introduces an approach for implementing code coverage analysis on TestCode libraries during test program development. By systematically measuring coverage, engineers can identify untested code paths, reduce the risk of latent defects, and improve the overall robustness of reusable components. The methodology provides greater visibility into library behavior, helping teams validate functionality more thoroughly before integration into production test programs. It also supports more consistent verification practices across projects, enabling scalable development as device complexity continues to increase. Overall, code coverage analysis serves as a key metric for strengthening quality assurance, improving confidence in shared libraries, and reducing debug effort, ultimately enabling faster and more reliable time-to-market for advanced semiconductor devices.

As AI chips continue to power high-performance computing, increasing integration density and the addition of complex IP blocks such as PCIe and HBM are driving rapid growth in register configuration space. This expansion can significantly extend verification cycles when using traditional ATE-based ATPG validation approaches, creating a need for more efficient workflows that accelerate bring-up, debug, and time-to-market. This presentation focuses on the UltraFLEXplus platform and summarizes real project practices for applying the Port Bridge verification tool to AI chip validation. It highlights how Port Bridge streamlines verification workflows, improves debug efficiency through visualization, and supports practical multi-port collaboration in complex device environments. The discussion begins with methods for establishing a scalable debug setup on UltraFLEXplus, including key configuration steps and proven procedures that improve day-to-day debugging efficiency. Next, driven by real-world HPC project requirements, we highlight the most frequently used and high-impact capabilities that deliver measurable efficiency gains, such as multi-port support and real-time debug feedback. In particular, we highlight on-the-fly V/I and frequency measurement at any target register, enabling faster debug iterations. Finally, it provides a data-driven comparison of process complexity and overall efficiency when using Port Bridge versus conventional vector conversion flows, illustrating where time and effort are reduced across the verification cycle. Overall, this work demonstrates the feasibility and effectiveness of Port Bridge for debugging and verifying advanced HPC-class devices and provides practical, reusable guidance that can be applied to similar AI chip verification challenges.

As device complexity continues to increase, ATE test programs are growing in size, driving the need for larger, more distributed engineering teams. To manage this complexity while maintaining development speed and quality, organizations are increasingly adopting automation and CI/CD practices within their test program workflows. This presentation provides practical guidance for integrating GitHub and Jenkins into test program development, enabling a more structured and scalable development environment. It highlights how Teradyne’s DevOps for Test framework supports collaboration, version control, and automated validation across teams of varying sizes. Key topics include Jenkins pipeline design and execution, leveraging dynamic agents to support both single and parallel pipelines across multiple jobs or workbooks, with the flexibility to run in either online or offline environments. The discussion also covers integration with Oasis tools to enhance test program quality, along with the incorporation of custom software components into the pipeline. Proven strategies are presented based on real project experience, including approaches that have successfully supported teams of up to 30 engineers while maintaining efficiency and consistency across development efforts. Overall, this work demonstrates how automation and modern DevOps practices streamline workflows, reduce manual effort, and significantly improve time-to-market for complex semiconductor test program development.

Teradyne DevOps for Test, or D4T, is an automated framework built on CI/CD principles to streamline semiconductor test program development. It uses source control as a single source of truth and triggers automated pipelines for both offline development and scheduled online validation, ensuring consistent integration and test program quality. These pipelines generate valuable artifacts such as logs, performance metrics, and device data, creating a continuous feedback loop for improving program reliability and efficiency. This presentation introduces the D4T Dashboard, which transforms pipeline outputs into actionable insights through a unified, interactive interface. By consolidating data from multiple pipeline executions, the dashboard enables teams to visualize trends, monitor development progress, and track quality metrics over time. The discussion demonstrates how device data from a UltraFLEXplus tester agent can be visualized within the dashboard, outlines the setup required to enable full functionality, and explains how to interpret the insights to guide development and debug decisions. By closing the loop between execution and analysis, the D4T Dashboard accelerates feedback cycles, reduces manual effort, and supports continuous improvement across the test program lifecycle.

Protecting intellectual property is critical to maintaining competitiveness and trust in the global semiconductor industry, where design and manufacturing are often distributed across multiple sites and partners. While hardware security has historically received significant attention, software-related risks in manufacturing test environments are becoming increasingly important. Test programs frequently contain sensitive data, including secure register configurations, proprietary algorithms, and device-specific patterns, which can be exposed through debugging tools or unauthorized access. Captured test patterns and manufacturing data also represent valuable assets that require strong protection. This presentation introduces enhancements to the IG-Secure solution within the Oasis toolset, designed to protect IG-XL test programs from unauthorized access. It outlines multiple levels of protection, identifies common vulnerabilities in test environments, and highlights mitigation strategies such as access control mechanisms and encryption. Practical examples demonstrate how different security levels can be implemented, including extended coverage for C# and .NET-based additions within IG-XL. These approaches enable organizations to better safeguard sensitive data throughout the test lifecycle. Overall, the solution supports stronger IP protection, improved compliance with security requirements, and increased confidence in secure test program deployment across distributed manufacturing environments.

The Teradyne CIS tester provides core image and data processing capabilities through the Image Data Processing Library, or IDPLib, enabling fast and efficient computation for image sensor testing. IDPLib includes commonly used functions such as image filtering and image-to-image operations, with all processing executed on the tester’s DSP PC. However, IDPLib has limitations when handling proprietary or highly specialized algorithms, as users cannot modify intermediate processing steps executed on the DSP. As a result, custom implementations often rely on per-pixel calculations using VBA, which can create significant performance bottlenecks and increase overall test time due to inefficient data handling. This presentation introduces an alternative approach that leverages add-in DLLs to perform complex image processing in a more secure and efficient manner. By implementing functions in a compiled C++ environment, the method delivers improved performance and scalability, particularly when working with large datasets and computationally intensive algorithms. The approach also addresses key considerations when using DLL-based solutions, including potential memory risks such as access violations and memory leaks, and outlines best practices for safe integration within the test environment. Overall, this methodology enables faster execution, greater flexibility for custom algorithms, and improved performance for advanced CIS testing applications, providing a practical framework for enhancing image processing workflows.

The adoption of C# .NET in IG-XL introduces new opportunities for applying modern software development practices to semiconductor test programs, such as structured unit testing. Establishing hardware-independent testing approaches is essential for improving code quality, accelerating development, and reducing reliance on limited test resources. This presentation shares practical techniques for building unit tests in an IG-XL environment using the TestHarness for .NET library, which enables test execution without requiring a full IG-XL installation. By combining MSTest for test organization, Moq for dependency simulation, and TestHarness for realistic IG-XL behavior, engineers can create reliable and repeatable testing frameworks that support multi-site scenarios. A consistent setup pattern is introduced to ensure each test starts from a clean and controlled state, improving reproducibility and minimizing variability. The discussion also covers commonly used unit testing patterns relevant to IG-XL development, such as validating multiple input conditions, verifying interactions with hardware abstraction layers, and configuring simulated responses to test edge cases and failure conditions. The approach enables early validation of multi-site execution logic, allowing engineers to detect issues before deploying to hardware and reducing overall integration risk. Overall, this methodology promotes the creation of fast, readable, and maintainable tests that clearly identify issues when they occur. It enables teams to build confidence in their code, streamline debugging, and accelerate IG-XL test program development while minimizing unexpected issues during production deployment.

IG-XL test program flows have become increasingly complex, making it difficult for engineers to quickly understand execution paths and determine how specific states are reached during development and debugging. This complexity can lead to longer debug cycles, reduced efficiency, and increased frustration when working with large or intricate programs. This presentation introduces the Flow Visualizer and Debugger Tool, an out-of-process utility designed to simplify navigation and debugging of IG-XL test program flows. The tool provides a graphical representation of program logic, allowing engineers to visualize execution paths and better understand flow behavior without disrupting existing workflows. It enables intuitive interaction with test programs through features such as breakpoint control and real-time data inspection, helping engineers trace execution step by step and gain insight into decision points within the flow. The modern interface supports efficient exploration of program structure and behavior, improving visibility into complex logic. By streamlining the debugging process and making program flows easier to interpret, the tool reduces time to resolution and enhances productivity for both new and experienced engineers. Overall, this solution establishes a more efficient and user-friendly approach to debugging, improving development workflows and supporting higher-quality test program delivery.

Supporting customer debugging requests for IG-XL test programs can be challenging when required data is not readily available. While test programs are typically easy to share, associated pattern files often contain sensitive intellectual property or are prohibitively large, with individual pattern files sometimes exceeding 1GB and total datasets reaching tens of gigabytes. These constraints can delay issue reproduction and extend the time required to diagnose and resolve defects. This presentation introduces a tool designed to enable efficient test program debugging without requiring access to original pattern data. The solution automatically parses the test program to extract key pattern information, including pattern names, label structures, module associations, and DSSC settings, and generates corresponding lightweight placeholder patterns consisting of minimal pattern lines. By creating minimal dummy patterns that maintain structural compatibility with the original test program, the tool allows engineers to execute and validate program flow without exposing proprietary data or transferring large files. This enables faster issue reproduction and accelerates the debugging process. The approach significantly reduces dependency on customer-supplied pattern data, improving responsiveness and enabling more efficient support workflows. Overall, the solution provides a practical method for overcoming data access and transfer limitations, allowing engineers to deliver faster, more effective debugging support while respecting intellectual property constraints.

Modern ATE workflows increasingly rely on protocol-level debug and validation scripts developed outside the ATE environment. These can include Python, C, C++, or even .NET. However, leveraging these existing scripts on ATE platforms typically requires significant conversion effort to port over to ATE software calls. This presentation introduces a new method for remote protocol programming through new remote proxies for the PortBridge API. This enables developers to reuse their existing scripts directly on the ATE without invasive and error prone porting. PortBridge normally operates within IG-XL as a C# .NET library. Our solution extends this by providing remote proxies for .NET Framework, .NET Core, Python, and C++. These proxies forward protocol commands to PortBridge, running in-process on the tester, allowing external programs to drive real hardware interactions while the system remains idle in IG-XL. With this approach, engineers can remotely run Python scripts, C++ executables, or other language-specific tools to record and debug protocol transactions directly on the device.

As device complexity increases, the volume of real-time data captured during test continues to grow across digital, DC, and RF instruments. Efficiently processing this data across multiple pins and sites is critical to maintaining performance and scalability in modern test programs. This presentation introduces new DSP method attributes, RunDspType.Site and RunDspType.PinSite, in IG.NET that enable real-time parallel processing of captured data across multiple sites and pins. These attributes support a more structured and efficient approach to handling large hardware-generated data streams within the DSP-PC environment. Captured data is managed using flexible data models that represent measurements at the site or pin-site level. These data structures are partitioned into smaller blocks based on site or pin-site grouping and distributed across multiple processing cores, allowing the DSP subsystem to achieve high levels of parallelism and improve overall processing efficiency. The approach simplifies implementation by providing a consistent framework for handling multi-dimensional data, reducing the need for complex custom logic. It also improves code readability, maintainability, and reuse, enabling engineers to develop more scalable and efficient test solutions. Real-world examples from DC, digital, and RF applications are presented to demonstrate how these methods streamline data processing workflows and improve execution performance. Overall, this capability enhances the efficiency of real-time data handling in IG-XL, enabling faster processing, cleaner code structure, and more scalable solutions for increasingly data-intensive test environments.

Modern semiconductor devices increasingly require adaptive, response-driven pattern execution, yet many legacy pattern generation flows remain limited to simple cycle-repeat structures. These limitations prevent teams from fully utilizing advanced UltraFLEXplus capabilities such as multi-bit match loops and dynamic branching, resulting in slower bring-up and less efficient debug cycles. To address this gap, an enhanced in-house pattern generation tool was developed to support these advanced features and modernize the workflow. This presentation describes how the upgraded tool analyzes legacy patterns, identifies DUT-dependent timing regions, and converts them into optimized multi-bit match loop structures that respond dynamically to device behavior. This approach reduces unnecessary cycles, minimizes manual intervention, and produces cleaner, more efficient patterns aligned with UltraFLEXplus execution. Key challenges are also discussed, including handling branch conditions under variable DUT responses and maintaining readable, production-ready outputs while integrating timeout and fallback logic. Addressing these challenges was essential to ensuring reliable, hardware-aware pattern generation. Overall, the solution demonstrates how advanced UltraFLEXplus capabilities can be effectively integrated into internal toolchains, providing a practical framework for modernizing test workflows and managing increasing device complexity.

Test program development often depends on running on hardware for final verification, which can create significant schedule pressure when issues are discovered late in the process. In addition, ensuring complete coverage of all test flow paths can be difficult, potentially impacting overall program quality. Enabling realistic offline testing can significantly improve productivity by allowing more thorough validation before silicon is available. This presentation introduces the Virtual Runtime Engine on the UltraFLEXplus platform, which enables execution of test programs offline using real or simulated data that accurately reflects online behavior. This capability allows engineers to validate test methods and flow logic without requiring immediate access to hardware. The solution supports multiple methods for generating response data, including recording actual program runs or programmatically creating data through an application interface. This flexibility enables engineers to simulate a wide range of test conditions and edge cases during development. By enabling more comprehensive offline validation, the approach reduces late-stage issues, improves program coverage, and accelerates development cycles. Overall, the Virtual Runtime Engine enhances test program quality while reducing dependency on limited hardware resources, helping teams deliver more robust and reliable test solutions within tighter schedules.

Since its introduction, IG-Correlate has continued to evolve through ongoing collaboration between Oasis developers and the core user community. As the tool has matured, its range of applications within test engineering workflows has expanded significantly. This presentation provides an overview of IG-Correlate’s capabilities and highlights common use cases that demonstrate its value in day-to-day test engineering activities. These include generating structured reports to format and analyze test program data, integrating with DevOps pipelines to automate test program evaluation, and leveraging interactive visualizations to assess overall program health. The discussion also illustrates how these use cases can be implemented within existing workflows, enabling teams to improve efficiency, consistency, and visibility across development and validation processes. As IG-Correlate continues to evolve through user-driven enhancements and development efforts, it further streamlines the pre-correlation process and strengthens its role as a key tool within the test engineering ecosystem.

GitHub Copilot is increasingly used to accelerate software development, but achieving consistent gains requires more than simply enabling the tool. This presentation shares practical lessons learned from hands-on experience and structured experimentation, focusing on how to effectively integrate Copilot into modern development workflows while maintaining code quality and consistency. The discussion covers how Copilot can be configured and used across common development environments, including Visual Studio Code and cloud-based workspaces, and how developers can improve results by providing clear and structured context. Techniques such as writing descriptive comments and defining intent at a high level are shown to guide Copilot in generating functional code, ranging from simple snippets to complete functions and class implementations. Beyond code generation, the presentation highlights practical use cases in refactoring, debugging, and code comprehension. It demonstrates how Copilot can assist with identifying issues, improving readability, and accelerating development across common domains such as data processing, automation, and DevOps workflows. The session also explores strategies for customizing Copilot behavior to align with project standards and individual coding styles. Approaches such as reusable prompt templates and persistent instruction files are discussed as ways to improve consistency, reduce repetitive input, and guide the tool toward preferred coding patterns. Finally, best practices for team adoption are presented, including methods for maintaining development standards, ensuring consistent outputs across contributors, and balancing speed with proper code review. Overall, the presentation provides a practical framework for integrating AI-assisted coding into everyday workflows, enabling developers to increase productivity while sustaining high-quality, maintainable software in real-world engineering environments.

Test program development for Ultra-Wideband applications is becoming increasingly complex, driving the need for more scalable, maintainable, and efficient software approaches. Migrating legacy test programs to modern programming environments can significantly improve development productivity and long-term supportability. This presentation describes the conversion of a UWB test program from VBT to C# .NET using IG-XL 11, highlighting the benefits of adopting a modern, object-oriented programming framework. The transition enables greater code reuse through integration with existing and new libraries, improves debugging efficiency, and enhances scalability through more readable and structured code design. These advantages contribute to reduced development effort and faster deployment of complex test solutions into production. The discussion covers the conversion of digital, analog, and RF test components, including continuous wave and modulated RF measurements. Example test cases include continuous waveform source and capture, modulated waveform source and capture, transmitter power, modulation accuracy and spectral mask. The conversion process also addresses integration of advanced DSP routines within the new architecture. The test implementation leverages a range of instruments, including RF, digital, and analog resources, demonstrating how the converted program operates within a complete test environment. Overall, the migration to C# .NET provides a robust framework for developing and maintaining advanced UWB test programs, improving code quality, reducing debug time, and enabling faster time-to-production for complex devices.

Accelerating silicon bring-up is critical for reducing development risk and meeting aggressive time-to-market goals. Traditional workflows often separate bench debug from production test environments, creating delays as engineers wait for packaged devices and transition between tools and platforms. This presentation introduces an approach that enables early core-level debug directly on Automated Test Equipment by integrating PortBridge with Lauterbach Trace32 tools. The solution bridges the gap between design validation and production test, allowing engineers to apply familiar debug workflows at the wafer level without waiting for final packaging. A key advantage of this approach is the ability to reuse existing debug methods and tools across both bench and ATE environments, improving workflow consistency and reducing integration effort. The system enables efficient pattern generation through Trace32-based recording, while supporting collaboration between design, software, and test engineering teams through a shared and unified debug environment. The discussion highlights how this integration streamlines bring-up activities by enabling real-time interaction with device cores and reducing the need for multiple validation cycles across different platforms. This results in faster issue identification and resolution during early silicon stages. A real-world implementation demonstrates measurable improvements in development efficiency, including a significant reduction in bring-up time, validating the effectiveness of the approach in production scenarios. Overall, this methodology reduces debug cycles, improves cross-team collaboration, and accelerates silicon validation, enabling faster product development while maintaining flexibility for ongoing enhancements and future device architectures.

Designing Device Interface Boards for semiconductor testing is a complex and time-intensive process, requiring engineers to map hundreds of device pins to appropriate test instruments while satisfying electrical, timing, and routing constraints. This process often involves iterative decision-making and manual optimization, leading to extended development timelines and increased risk of design errors. This presentation introduces a machine learning-based approach to optimizing resource allocation in DIB design for both analog and digital device testing on ETS-800 and UltraFLEXplus platforms. The solution leverages a structured framework that automates key steps in the design process, reducing reliance on manual iteration. The methodology consists of a two-stage workflow. The first stage focuses on intelligent instrument selection using a scoring system informed by domain expertise and heuristic evaluation. The second stage performs resource-aware channel assignment, enabling efficient utilization of available hardware while meeting design constraints. By combining machine learning techniques with expert-driven rules, the framework improves decision consistency and accelerates the design process. It enables more accurate mapping of signals to resources and reduces the likelihood of design inefficiencies that can lead to costly board revisions. Results from this approach demonstrate a significant reduction in development time, transforming a process that traditionally takes days into one that can be completed in a matter of hours. In addition, the improved allocation strategy enhances overall design quality and supports more efficient test execution. Overall, this solution provides a scalable and practical framework for modernizing DIB design workflows, improving productivity, and enabling faster deployment of test solutions for increasingly complex semiconductor devices.

In semiconductor manufacturing, trimming is a critical process used to adjust internal device parameters by programming trim codes to meet target specifications. This step compensates for process variations and ensures consistent device performance. However, implementing efficient trimming routines across multiple sites presents challenges in both accuracy and overall test time. This presentation introduces a general-purpose trimming framework designed for flexibility, scalability, and ease of integration across diverse test applications. The solution is based on an efficient binary search approach that determines the optimal number of trim iterations within a user-defined range and identifies the most accurate trim code. The algorithm dynamically adjusts search boundaries based on measurement results for each active site and removes sites from the process once they meet defined criteria. This adaptive approach allows all sites to be processed in parallel while minimizing unnecessary iterations, significantly improving test efficiency. The framework is implemented as a reusable module that can be deployed across multiple instruments and integrated with different test methodologies, including both protocol-aware and PortBridge-based environments. Overall, the approach enhances trimming accuracy, reduces overall test time, and provides a scalable solution for high-volume semiconductor production, enabling more efficient and consistent device calibration across a wide range of applications.

Managing Teradyne's diverse software ecosystem presents significant challenges for test engineers and administrators. With critical tools distributed across eKnowledge, users face a complex web of version dependencies, compatibility requirements, and discovery barriers. This complexity is amplified when supporting multiple IGXL versions, each requiring specific tool version alignments, creating administrative overhead and potential configuration errors. Teradyne’s centralized configuration platform is designed to eliminate this complexity through unified software management. Our solution provides a single interface for discovering, installing, and managing all Teradyne tools while maintaining version compatibility across the ecosystem. The platform features an intelligent recommendation engine that suggests relevant tools based on user workflows and installed configurations, helping engineers discover productivity-enhancing utilities they might otherwise overlook. Built on an extensible plugin architecture, the platform enables seamless integration of custom tools and third-party utilities, allowing organizations to tailor their software environments while maintaining centralized oversight. Tools can broadcast their operational status to provide real-time system health monitoring. For air-gapped environments, the platform includes enterprise deployment capabilities, enabling IT administrators to distribute curated tool packages and updates while maintaining security protocols. This comprehensive approach transforms software management from a fragmented, time-consuming process into a streamlined workflow that maximizes engineering productivity and reduces configuration-related downtime.

Semiconductor test operations increasingly generate diverse datasets, and many of these data sources do not follow the Standard Test Data Format (STDF). While PDF Exensio includes strong native support for STDF, many customers still produce proprietary ASCII-based datalogs driven by legacy flows or operational requirements. These non-standard formats can slow down data onboarding and create barriers to consistent ingestion and scalable analysis. This presentation introduces a streamlined method for converting customer-specific ASCII datalogs into a structure compatible with the PDF Exensio import workflow. The approach begins with an automated preprocessing step that prepares the required execution context and metadata. Exensio’s configurable import tools are then used to map key fields, including test names, test numbers, site information, and parametric results. Once defined, the data-definition configuration can be saved and reused, enabling future datalogs in the same format to be ingested with minimal incremental effort. By enabling repeatable ingestion of non-STDF ASCII datalogs, this approach reduces engineering overhead, accelerates time to analysis, and expands PDF Exensio’s usefulness as a flexible analytics platform across a wide range of customer-defined datalog formats.

Accurately testing a device is always the primary concern. However, once accuracy is achieved, the focus shifts to minimizing test time. Understanding what contributes to test accuracy can also reveal how to make the test time faster. Accuracy in an EVM test can be influenced by various settings, including instrument parameters such as gain, FS, and IF values. One often overlooked setting is modulation density, or QAM level. Under challenging conditions, such as low power where the signal-to-noise ratio (SNR) is compromised, using a higher-order QAM like 4096 QAMoften leads to inaccurate EVM measurements. This presentation will cover selecting the correct waveform used to test the device under the current conditions. How to choose the proper sample rate and intermediate frequency based on modulation bandwidth. How to evaluate the constellation diagram to help determine the cause of poor EVM performance. Finally practical methods to reduce test time. Conversely, employing a lower-order QAM, such as 16QAM, under the same conditions can still yield accurate results. Once accuracy is established, users can evaluate whether different test time reduction techniques affect measurement precision. The most effective way to reduce test time is by decreasing the number of processed samples, which can be achieved by limiting the time component of the test and/or lowering the sampling rate. After optimizing modulation test time, the final consideration for reducing test time involves streamlining program flow and efficiently utilizing DSP computers. Prioritizing accuracy first builds confidence in test results, enabling a logical approach to reducing test time. Ultimately, this leads to cost savings by shortening test duration while maintaining the highest possible yield accuracy.

Testing next-generation wireless devices such as Wi-Fi 7 and LTE requires advanced methods to manage increasing RF complexity while maintaining high throughput in production environments. Achieving accurate measurement performance while reducing overall test time is a key challenge for high-volume manufacturing. This presentation describes the development and optimization of Wi-Fi 7 and LTE test solutions on the UltraFLEXplus platform using an x16 DIB configuration with multiple RF resources. The work focuses on improving efficiency while maintaining high measurement accuracy for advanced modulation schemes and wide bandwidth requirements. Key challenges addressed include reducing test time and validating critical RF parameters such as wideband operation and high-order modulation performance. To meet these requirements, a customized RF library was developed to streamline both test execution and program setup, enabling more efficient handling of complex measurement routines. The discussion also highlights evaluation methodologies for signal quality, including the use of specialized test configurations to validate performance under demanding conditions. Lessons learned from the project are shared, including considerations for DIB design and limitations encountered in RF instrumentation, providing practical guidance for future implementations. Measured results demonstrate significant improvements in both efficiency and parallel performance across test flows, showing notable reductions in test time while maintaining high throughput and consistency. Overall, this approach provides a scalable and optimized test solution for advanced wireless devices, supporting efficient production testing of emerging communication technologies.

Test requirements for modern electronic devices continue to grow in complexity, demanding higher measurement accuracy, increased channel density, and support for advanced device architectures. Addressing these evolving needs is critical for maintaining performance and efficiency in high-voltage test environments. This presentation introduces the UVI96, a high-voltage instrument designed to meet these requirements while improving overall test efficiency. Building on the foundation of the UVI264, the UVI96 incorporates a floating instrument architecture that supports demanding applications through integrated high-voltage channels, time measurement units, differential voltage measurement capabilities, and precision reference sources. The discussion provides an in-depth overview of the instrument’s key functional blocks and their roles within the system. It also explains the implementation of the floating architecture, enabling operation across a wide voltage range, and outlines strategies for managing and balancing current in this environment to ensure stable and accurate measurements. Example applications are presented to demonstrate how this architecture supports real-world high-voltage testing scenarios, highlighting improvements in accuracy, flexibility, and system efficiency. Overall, the UVI96 provides a scalable solution for advanced high-voltage testing, enabling engineers to address increasingly complex device requirements while maintaining precision and performance in production environments.

Automotive millimeter-wave radar has become a key sensing technology for advanced driver assistance systems, relying on Frequency-Modulated Continuous Wave (FMCW) signals to accurately measure object distance, velocity, and angle. As these systems move into high-volume production, validating FMCW performance presents significant technical challenges. Critical chirp parameters such as sweep bandwidth, frequency slope, chirp cycle time, and integral non-linearity directly impact radar accuracy and system reliability. At the same time, operation in the mmWave frequency range requires precise frequency conversion and calibration, high-speed data capture to support rapid chirp acquisition, and tight timing synchronization to ensure accurate measurement. This presentation introduces a comprehensive FMCW test solution built on the UltraFLEXplus platform, utilizing UltraWave24G and DX81 instruments. The approach covers the complete test workflow, from hardware architecture to software implementation. Using IG-XL software and embedded DSP processing, the system captures down-converted FMCW chirp signals, performs digital IQ demodulation, and reconstructs the frequency modulation profile to extract key performance metrics. The discussion demonstrates how these techniques enable accurate measurement of sweep bandwidth, frequency slope, and integral non-linearity, while maintaining efficiency suitable for production environments. Validation results highlight the stability, scalability, and repeatability of the solution, demonstrating its ability to support high-performance mmWave radar testing in high-volume manufacturing.

MicroLED technology is gaining increasing attention due to its advantages in power efficiency, brightness, robustness as an inorganic solution, and scalability for emerging applications such as augmented and virtual reality. It is becoming a key enabler for next-generation display systems and is also attracting interest in short-range data communication, where it offers simpler integration compared to laser-based solutions. Despite these advantages, testing MicroLED devices presents significant challenges. The technology is still maturing, and the high density of emitters per wafer introduces substantial complexity in measurement and data handling. For applications such as AR and VR, additional challenges arise from low optical coupling efficiency into waveguides and the need to characterize performance in a way that reflects human visual perception. This presentation explores the key challenges associated with MicroLED testing and examines current approaches to overcoming these limitations. It discusses strategies for managing high device counts, improving measurement consistency, and adapting test methodologies to capture both electrical and optical performance accurately. The discussion also highlights considerations for scaling test solutions to support volume manufacturing, where throughput, repeatability, and yield optimization are critical. Overall, this work provides insight into the evolving test requirements for MicroLED technology and outlines practical approaches that support its transition from emerging technology to mature, high-volume production.

AC switching testing of power devices such as SiC, MOSFETs, and IGBTs is essential for evaluating dynamic performance, including switching speed and power loss. However, these tests inherently involve high risk, particularly when operating near device limits or under mismatched conditions. In such scenarios, excessive current or latch-up effects can occur, potentially leading to device damage or complete failure. This presentation addresses the challenge of overcurrent-induced failure during AC switching tests and introduces a protection approach designed to improve test safety and reliability. It begins by examining the underlying mechanisms of latch-up and identifying the conditions that can trigger destructive events during high-stress testing. Based on this analysis, an overcurrent protection circuit is presented as a key safeguard within the test system. The circuit monitors current conditions in real time and rapidly disables the device under abnormal conditions by blocking the drive signal, preventing further escalation and protecting the device from damage. Key design considerations are discussed, including detection sensitivity, response timing, and integration with the test environment to ensure reliable operation under fast transient conditions. Experimental results demonstrate that the proposed protection approach can detect overcurrent events accurately and respond quickly enough to prevent catastrophic failure. Overall, this solution enables safer and more robust AC switching testing, allowing engineers to evaluate device performance under demanding conditions with reduced risk, improving test reliability and protecting valuable devices during characterization and production testing.

Accurate capacitance and resistance measurements are essential for evaluating device switching performance and reliability in semiconductor production. At the wafer level, parameters such as input capacitance and gate resistance are particularly sensitive and require both high precision and efficient measurement techniques to support high-volume manufacturing. This presentation describes the development and optimization of parallel measurement techniques for input capacitance and gate resistance on large-diameter wafers. Traditional serial measurement approaches often result in long test times, limiting overall productivity and throughput. To address this challenge, a parallel measurement configuration using multiple LCR instruments is implemented to improve efficiency while maintaining measurement accuracy. The approach enables simultaneous data acquisition across multiple channels, significantly reducing total measurement time. In addition, methods for achieving stable gate resistance measurements on large wafers are examined, with a focus on calibration strategies and grounding techniques to ensure repeatable and reliable results. The results demonstrate practical solutions for improving both performance and efficiency in wafer-level capacitance and resistance testing. Overall, this work provides a scalable approach to enhancing test throughput while maintaining precision, offering valuable guidance for high-volume semiconductor production environments.

Traditional hardware architectures for power and discrete applications often rely on a centralized PCB design, where peripheral modules function primarily as supporting circuit blocks. While effective, this approach can introduce limitations related to scalability, integration complexity, and single points of failure. This presentation introduces a decentralized hardware architecture that redefines this model by embedding independent control within each module and connecting them through a standardized interface. This structure enables flexible stacking, scalable system configuration, and improved modularity, eliminating many of the constraints associated with centralized designs.A key element of the approach is the development of a modular controller that operates within a floating power domain, allowing improved isolation and mitigation of noise-related challenges typically seen in ground-referenced designs. This enables more reliable operation while simplifying system integration by removing the need for shared control routing through a central board. The hardware modules are designed with a compact, card-based form factor that supports platform-level standardization and ease of reuse across different applications. This modular design approach reduces design iteration effort, improves system maintainability, and enhances fault isolation at the module level. Comparative evaluation shows that the decentralized architecture reduces integration complexity and accelerates development cycles while improving reliability and scalability. Overall, this approach provides a more robust and flexible foundation for future hardware system development, enabling scalable expansion, simplified design processes, and improved long-term performance.

Testing 6-in-1 power modules presents significant challenges due to parasitic inductance and capacitance introduced by the socket and Device Interface Board. These parasitic effects can lead to oscillations and measurement variation across phases, requiring careful design consideration and extensive validation during development. This presentation introduces a practical and cost-effective approach to improving measurement stability for multi-phase power modules. The method leverages existing 2-in-1 test assets and applies a multi-touchdown measurement technique to isolate individual phases during testing. By reducing the influence of parasitic elements, the approach effectively suppresses oscillations and improves the consistency and reliability of measurement results across all phases. It also minimizes the need for complex DIB redesigns and extensive upfront validation, helping to streamline development workflows. The discussion highlights key considerations for implementing this method, including test setup strategies and measurement sequencing to ensure accurate phase isolation. Overall, this solution provides a scalable and low-cost method for improving measurement accuracy and reliability in advanced power device testing, supporting more efficient validation and production of increasingly complex multi-phase modules.

The widespread adoption of 48 V power architectures in electric mobility is driving the need for accurate validation of power modules to ensure performance, robustness, and safety. This presentation describes a structured test methodology for an 80 V power module, with a strong focus on minimizing parasitic inductance in the test setup to achieve reliable measurement results. Electrical performance is evaluated through efficiency measurements, AC and DC parameter characterization, and dynamic response analysis under both steady-state and transient operating conditions. Particular attention is given to the physical implementation of the test environment, demonstrating how reducing loop inductance at the input, output, and instrument connections is critical to minimizing voltage overshoot, ringing, and unintended triggering of protection mechanisms during high di/dt events. Protection functions, including overcurrent and short-circuit protection, are also validated as part of the overall test approach. The methodology highlights best practices that improve measurement repeatability and strengthen correlation with real-world electric mobility operating conditions.

This presentation introduces a high-voltage instrumentation platform designed to deliver up to 8 kV for advanced off-state characterization of Silicon Carbide power devices. As device breakdown voltages continue to increase into the multi-kilovolt range, test environments require higher voltage sourcing capability, improved isolation, and enhanced measurement capability. The platform is engineered to address these requirements, enabling precise and repeatable evaluation of key off-state parameters such as BVDSS and IDSS. It incorporates integrated protection mechanisms and programmable voltage ramp profiles to ensure safe operation and consistent measurement results across a range of test conditions. Designed for integration into automated ATE systems, including ETS-88, the solution supports synchronized control interfaces, safety interlocks, and configuration options suitable for both characterization and production testing flows. Overall, the instrument addresses a critical need in high-voltage testing by providing a scalable and reliable solution for next-generation Silicon Carbide device development, reliability screening, and high-volume manufacturing.

Silicon Carbide devices are rapidly replacing traditional silicon-based technologies in high-power applications such as electric vehicles and solar energy systems. At the same time, the rising power demands of AI data centers are driving a shift toward high-voltage DC architectures, where SiC devices, with their strong performance at 800 V and beyond, are becoming key enablers. These applications require exceptional reliability, making accurate evaluation of short-circuit withstand capability and high-current performance essential for long-term system stability. This presentation examines the challenges associated with short-circuit testing of SiC devices, driven by their material properties and fast switching behavior. Short-circuit currents can reach several times the rated current, with extremely high di/dt and dv/dt conditions that require test systems capable of delivering high peak currents while maintaining low parasitic inductance. These conditions also introduce significant electromagnetic interference, placing additional demands on gate driver design and measurement stability. The discussion introduces a high-power ATE-based testing solution designed to address these challenges. The approach enables accurate measurement of high current levels in short-circuit conditions while maintaining system stability and measurement fidelity. Special attention is given to overcoming voltage drop effects during high-current testing and extending the performance limits of the test system to meet demanding application requirements. In addition, the solution evaluates gate driver performance under extreme conditions, focusing on isolation and noise immunity to ensure reliable operation during fast switching events. Overall, the methodology provides a robust framework for validating critical reliability characteristics of SiC devices, supporting their deployment in next-generation electric vehicles and AI data center power systems while enabling scalable, high-volume production testing.

Arcing during high voltage power semiconductor wafer testing has been an issue for decades. Vehicle electrification and the growing AI power requirements are accelerating adoption of WBG technologies that are quickly expanding into higher voltages and power densities. To meet these new market needs, the requirements are changing. These device types are: • Increasing power density, decreasing device geometries • Migrating to larger wafers (300mm), higher parallel test site count needed • Improving system efficiency, faster switching speeds • Maturing technologies, lower wafer yields These technical needs coupled with the business need of scaling high voltage devices to service the market demand are driving the incident rate and severity of arcing at wafer test. In this presentation, we will review the market trends, types of arcing on wafer, the impact of arcing to the system/wafer, standard mitigation risks, energy management techniques, and finally the technical/business tradeoffs.

The rapid growth of AI servers and large-scale GPU clusters, with power consumption exceeding 100 kW per rack, is driving significant transformation in the Power Management IC market. This trend is accelerating demand for highly efficient and integrated solutions such as high-performance DrMOS devices, positioning the AI server segment as a key growth driver for next-generation PMIC technologies. Testing high-current DrMOS devices presents several technical challenges. One of the most critical is the accurate measurement of ultra-low on-resistance, or RDS(on), which can be significantly affected by parasitic resistance and self-heating. Addressing these challenges requires advanced techniques such as short-pulse measurements and Kelvin sensing methods to ensure measurement accuracy. This presentation highlights testing solutions designed for high-power and high-current applications, including DrMOS and smart power stages. It explores how these approaches address key measurement challenges and improve test accuracy and efficiency, with a focus on enabling reliable validation in demanding production environments.

The HSD 64 was released on the ETS 800 platform in 2024. While an introductory paper was published (Introducing the HSD-64 for the ETS-800), this paper aims to provide an instrument deep dive following its official release. With doubled channel density over the HSD-32, the HSD 64 improves site count efficiency and reduces cost of test (COT), but significant advances lie in its expanded feature set. This includes features like DSSC multi engine, which enables asynchronous and layered device communication protocols; DIB Access, which is a 1:8 style multiplexer with fanout capability; and software emulation mode for applications developed on the HSD-32. Compatibility remains central; therefore, an in-depth discussion is provided on the HSD 64’s emulation performance modes and limitations, detailing emulation behaviors for APIs and pattern-based operations. Additionally, a variety of performance data topics will be discussed, covering topics like DC accuracy improvements, memory capacity, and pattern execution times. This deep dive equips users with practical guidance for maximizing HSD 64 value while ensuring smooth adoption from legacy HSD 32 applications.

This presentation summarizes the capabilities and initial performance results of the OMS instrument, highlighting its role in precision measurement applications such as battery management systems, voltage references, and other power management devices. The OMS maintains hardware and API-level compatibility with QMS, allowing it to occupy the same slot with minimal system changes. Existing QMS channels can be mapped to OMS through a simple configuration update, enabling a smooth transition within existing test environments. To achieve high measurement accuracy, the OMS is calibrated using precision instrumentation, including a Keysight 3458A digital multimeter, a Fluke 732C voltage reference standard, and a dedicated calibration DIB. The OMS features eight channels, each integrating a high-resolution 24-bit ADC, a high-speed 14-bit ADC, and a 20-bit reference DAC. The architecture allows concurrent operation of ADCs and DACs, supported by a temperature-stabilized voltage reference with both automatic and on-demand self-calibration capabilities. Initial performance results are presented, demonstrating measurement accuracy, stability, and overall system capability across a range of precision applications.

Executing high-current AWG patterns on the ETS-800 platform introduces challenges in maintaining stable SPMB booster rail voltage without negatively impacting overall test time. Traditional approaches rely on manually inserting delays and tuning them through iterative adjustments, often resulting in excessive wait times and reduced efficiency. This presentation introduces an adaptive solution for dynamic booster rail management that optimizes performance during AWG pattern execution. The method analyzes the user-defined AWG pattern prior to execution to predict expected voltage discharge behavior and determine the required rail voltage for proper operation. Based on this prediction, the algorithm applies only the minimum delay necessary for the rail to recharge, avoiding unnecessary idle time. During execution, the system continuously monitors the rail condition and dynamically adjusts timing to ensure the target voltage is achieved, eliminating the need for manual tuning. In addition, the solution provides visibility into the recharge time applied, enabling users to further optimize test flow sequencing and improve overall efficiency. Overall, this adaptive approach minimizes delay overhead, reduces total test time, and simplifies implementation, providing a more efficient and user-friendly method for maintaining rail stability during high-current test operations.

The ETS-800 platform is a leading ATE solution for power stage device testing, and this presentation introduces key test methodologies for these applications. It begins with an overview of a recently developed power stage prototype demo kit designed to enable faster response to technical inquiries and support rapid experimentation. The demo kit features a standard rider and connector-based interface built on a Rapid Proto Daughter Card, allowing shorter development lead times compared to traditional full daughter card solutions. This approach enables execution of critical tests using established DIB designs and instruments, accelerating validation and improving confidence in the overall test solution architecture. By providing faster feedback on device-specific requirements, this solution enhances the ability to evaluate and optimize test strategies across a range of power stage devices. In addition, this presentation highlights the SPU-8112 instrument and examines its advantages in testing power stage devices, including key findings that demonstrate its effectiveness in high-power, high-current applications.

Engineers working with the ETS-800 platform can benefit from a deeper understanding of its new capabilities, including bus connections, force and sense shorts, local Kelvin connections, bank mode, SPU driver mode, APU32 150k Kelvin resistors, UPD64 SH connections, and QMS force voltage pedestal-out functionality. This presentation clarifies these features and demonstrates how they can be used to perform contact resistance measurements, DIB diagnostics, and Kelvin checks without the need for additional hardware on the DIB. It covers multiple Cres measurement techniques, including the use of SPU driver mode to achieve approximately 1 ohm accuracy, the SPU parametric kelvin feature, and the use of bank mode with both APU and UPD resources to measure Cres for both high and low, force and sense connections. It also provides a detailed explanation of driver mode behavior, including how sense pins can still be utilized, along with a discussion of spu2112kelvinmode(), and the HSD64 DIB access bus. The discussion also explains how to perform Kelvin checks during continuity testing using APU32 150k Kelvin resistors. It then highlights the advantages of performing open socket load board checks on ETS-800 and demonstrates several methods for validating different components, particularly in configurations involving Kelvin connections. In addition, the presentation describes how both software and hardware features of the ETS-800, such as per-pin APU clamps, can eliminate the need for external resistors between force and sense connections. Finally, it reviews the test time impact of applying these techniques for validating contact resistance, Kelvin connections, and overall load board functionality, and includes selected customer examples and auto-generation tool experiences.

Multi-site index parallel testing represents an advanced approach in Automated Test Equipment, enabling higher throughput and reduced cost compared to traditional multi-site methods. By optimizing how devices are processed and indexed through the test flow, this technique improves overall system efficiency, particularly for devices with short test times. This presentation introduces multi-site index parallel testing and its implementation on the ETS-800 platform with supporting handler integration. The approach focuses on maximizing units per hour while minimizing the required tester configuration, allowing more efficient use of capital equipment. Beyond test execution, the methodology integrates downstream processes such as laser marking, automated optical inspection, and tape-and-reel handling into a streamlined production flow. This level of automation reduces manual intervention, shortens production cycles, and lowers overall manufacturing costs. The discussion outlines the implementation of index parallel functionality and highlights key considerations for deploying this approach in production environments. It also shares insights gained during development, including system integration challenges and optimization strategies. Overall, this approach demonstrates how coordinated test and handling automation can significantly improve productivity, reduce operational costs, and support scalable, high-efficiency mass production solutions.

Relay selection, usage, and maintenance play a critical role in achieving reliable and efficient ATE performance. This presentation provides a review of several relay technologies use in ATE DUT interface board design such as mechanical relays, solid-state relay solutions and mux alternatives. The discussion begins with mechanical relay types including telecom, automotive, 50-ohm controlled impedance and reed relays. It covers key characteristics such as contact materials, temperature performance, switching speed, longevity, suppression diode usage, parasitic effects, and on-resistance. Additional topics include load board validation, parasitic capacitance, space optimization, destructive hotswitching, as well as beneficial low-current hotswitching which reduces failure rates. Practical considerations such as bi-metallic effects in reed relays, techniques for unsticking relays, and characteristics of single-stable and automotive-grade relays are also explained, along with differences between Form A, B, C, and D configurations. The presentation also examines multiplexers, looking into switching speed, trench isolation and when muxes may be preferred over relays, particularly for high-impedance nodes. Photomos relay technologies are covered in detail, including discussing the fast on, fast off accelerator circuit, CxR5 and CxR10 output types, form A strand configurations, form B configuration options, simple Form C photomos circuits (with and without Break Before Make guarantees). The examination continues, delving into back-to-back vs. parallel body diode output connections, longevity, fast edge performance, T-switches, leakage, hotswitching resilience, overvoltage damage, drive circuit considerations including photodiode voltage, max drive current, high temperature photo-diode overdriving benefits, and board space considerations. This discussion also examines to Capacitor Coupled MOS relays. Finally, the presentation reviews internal CBIT drive circuits, including key characteristics and practical design considerations to prevent unintended behavior in fault conditions.

Device complexity continues to scale upward as time to market demands shrink. Efficiency during development is more critical than ever. Teradyne has released a broad range of new software features for the ETS-800 platform that improve development efficiency for a wide variety of device types over the last few years. But many teams are not aware of these features or how to use them on new applications. This includes features that are designed to reduce overall coding effort, improve debug efficiency, and also allow users to become more proficient with MST software in a shorter amount of time. This presentation will explain the benefits of these new features and show how to easily implement them in your next development project. Topics to be included are Pins-Not-in-Same-State, Per-Pin-Forcing, Incremental Programming, Pin Grouping/Instrument Site Sharing, ETS Quick Access Bar, Enhanced Alarm Reporting, eDST and PDS equation support, and others.

Traditional protection techniques for DIBs and ATE instrumentation commonly use Zener diodes or transient voltage suppressors to clamp voltage during fault conditions. While these components can provide effective protection, they introduce trade-offs, including high current flow during conduction, increased parasitic capacitance, and leakage currents that can negatively impact low-level measurement accuracy. This presentation introduces an innovative and revolutionary alternative protection approach based on depletion-mode MOSFETs, offering a different method for safeguarding tester channels, DIB hardware, and devices under test. These devices enable controlled current limiting without relying on conventional voltage clamping behavior, helping to reduce the impact on measurement performance. This innovative approach addresses key limitations of traditional protection methods by minimizing excess current flow and reducing leakage effects, while maintaining the integrity of sensitive measurement paths. Additionally, the solution is self-contained and does not require external biasing or complex circuitry, simplifying implementation within existing designs. It is also capable of handling overvoltage conditions beyond typical compliance levels. This presentation will show how this method can be applied across a range of common circuit protection scenarios, providing a practical alternative for improving reliability and measurement performance in advanced test environments.

The rapid growth of AI and high-performance computing is driving data rates beyond the limits of traditional electrical interconnects, accelerating the adoption of silicon photonics and co-packaged optics. As these technologies transition to high-volume production, final test introduces new challenges that require precise, repeatable, and high-throughput validation of optical performance. This presentation introduces a co-packaged optics final test platform designed to meet the unique requirements of silicon photonics devices. The solution integrates optical measurement capability, robotic automation, and coordinated system design to create a scalable and production-ready test environment. A key focus is the integration of automated handling and alignment with high-precision optical instrumentation. The system combines robotic motion control with accurate electro-optical measurement, enabling consistent positioning and repeatable test execution while reducing manual intervention and variability. The discussion highlights the key elements required to deliver a cohesive test solution, including mechanical design, optical interfaces, motion control strategies, and coordinated software control. It also covers critical enabling technologies such as alignment methodologies, fixture design, automation workflows, and error-handling strategies tailored to optical devices. Lessons learned from early development and system integration are shared, illustrating the importance of aligning expertise across optics, automation, and test engineering to achieve reliable and scalable solutions. Overall, this approach provides a practical framework for enabling high-volume testing of silicon photonics devices, supporting next-generation AI infrastructure with improved efficiency, reliability, and manufacturability.

The Silicon Photonics market is expanding rapidly as data-centers, AI infrastructure providers, and high-performance computing systems increasingly rely on optical interconnects to overcome bandwidth and power limitations. Market forecasts show the sector reaching $8.13billion by 2030, driven by transceivers, CPO, and PICs. Together with the fabrication and packaging for silicon photonics getting matured, this growth is creating a critical need for scalable, automated electro-optical testing to support mass production. This presentation will give a brief overview of how Teradyne plays a central role in enabling this transition by leveraging our semiconductor ATE expertise and expanding into Photonics Test, to provide the high-throughput wafer-level and module-level test systems required for mass production. Introducing UltraFLEXplus Silicon Photonics Instrumentation: Photon100, including software and hardware capabilities. Effective silicon photonics testing directly impacts yield, reliability, and cost, enabling early defect detection, faster process learning, and consistent high-volume manufacturing of optical components.

In Silicon Photonics test applications, simultaneous optical and electrical probing is essential to reducing manufacturing costs by identifying defects early in the process. Testing of Silicon Photonics devices involves different probing configurations: electrical and optical probing on the same side of the wafer (Insertion 1) and electrical and optical probing on opposite sides of the wafer (Insertion 2). Such configurations introduce additional challenges in alignment, measurement precision, and test integration. This presentation will cover an Insertion 1 silicon photonics testing solution. The approach utilizes vertical electrical probe pins alongside an optical fiber array unit (FAU) designed to deliver multiple optical signals to corresponding grating couplers on the wafer. The FAU consists of optical fibers arranged with high precision to align with the grating coupler positions. This configuration enables simultaneous coupling of light into and out of the device, supporting efficient electro-optical measurement during testing. To achieve accurate and repeatable results, the optical coupling system is positioned with sub-micron precision independently of the electrical probing alignment. This decoupled alignment approach allows for optimized optical signal strength and improved wavelength-specific measurement accuracy without compromising electrical contact integrity. The presentation also discusses key design considerations for integrating optical and electrical test components into a unified system, including alignment strategies, fixture design, and measurement coordination. Example measurement results are included to demonstrate the effectiveness of the approach in enabling reliable and high-precision electro-optical testing. Overall, this solution provides a practical framework for testing silicon photonics devices with integrated optical and electrical interfaces, supporting accurate characterization while addressing the unique challenges of combined electro-optical measurement in advanced semiconductor applications.

In recent years, "Silicon Photonics" and "Co-Packaged Optics" have become as prominent in semiconductor industry reports and headlines as "AI." Silicon photonics test equipment, unlike almost every other technology in the test industry, is being designed and built before the standards are even written. This presents a unique gap between the design and test of silicon photonics, where the technology and standards are both on the bleeding edge. This presentation aims to educate test engineers on the physics of silicon photonics, the driving factors in popularity, industry-wide technological roadblocks, and the test challenges we are committed to solving. Finally, we will talk about upcoming silicon photonics technologies on the horizon to give you a preview of what we're hoping to see over the next 5 years. By the end of this presentation, you will have a baseline knowledge of silicon photonics technologies and the business drivers therein, understand key challenges in its design and test, and have an outlook on how silicon photonics will evolve in the future.

As customer products become more complex, there is an increasing demand for advanced test cell solutions that can accelerate time to volume production. Time to market remains a critical factor for success, especially as image sensor applications expand beyond mobile devices into a growing range of industries. This presentation provides an overview of the evolving image sensor market and highlights key drivers influencing test requirements. It then examines the capabilities of the UltraFLEXplus IPQx platform, including parallel test efficiency, illuminator size, and overall test cell architecture. The discussion addresses technical challenges associated with integrating image sensor probers, which are typically larger and more complex than standard chip probers. It outlines the simulation, analysis, and engineering solutions developed to enable effective docking and system integration. Verification results are presented to demonstrate the effectiveness of the final design, supported by visual demonstrations that illustrate real-world implementation. Finally, the presentation includes a comprehensive set of part numbers for the IPQx production solution to support straightforward deployment and adoption.

As AI and high-performance computing systems continue to evolve, device architectures are shifting from single-function components, such as GPUs or switches, to highly integrated heterogeneous packages composed of multiple chiplets. These advanced configurations may include high-bandwidth memory, compute devices, interconnect interfaces such as UCIe, and additional integrated components, all combined within wafer- or panel-level integration schemes and ultimately assembled into complete system packages. This increasing level of integration significantly raises test complexity, introduces new interdependencies between components, and expands the number of required test insertions throughout the manufacturing flow. Ensuring both known-good-die and known-good intermediate assemblies, such as chip-on-wafer or chip-on-panel structures, becomes critical for maintaining yield and controlling overall cost of test. This presentation provides an overview of these emerging integration trends and the resulting challenges for semiconductor test. It discusses how traditional test approaches must evolve to address increased device complexity, expanded test coverage requirements, and the need for improved coordination across multiple test stages. The discussion highlights new test strategies designed to balance coverage, cost, and throughput, while ensuring high quality and reliability in the final packaged product. Emphasis is placed on approaches that optimize yield at each insertion point and enable efficient validation of both individual components and integrated systems. Overall, the approach helps address the growing demands of next-generation AI and high-performance computing devices, supporting scalable test solutions for increasingly complex heterogeneous integration flows.

This presentation addresses the resolution of wafer test temperature inconsistencies observed during wafer-level testing. While hot (90 °C) and cold (−30 °C) conditions met specifications, room-temperature measurements were consistently ~1 °C lower than expected, adversely impacting yield—particularly at the wafer edge. Several corrective actions were evaluated, including extended soak times, purge air supply adjustments, probe card stiffener material changes, and insulation enhancements; however, none effectively improved temperature accuracy. Root cause analysis identified inaccuracies in the wafer prober chuck temperature sensors at 30 °C. Sensor variation led to erroneous averaged chuck temperature readings, resulting in the observed discrepancy. The issue was resolved through recalibration of the chuck temperature sensors and application of an approximate 1 °C heater offset. This correction restored temperature accuracy and improved test consistency. Following implementation, the UltraFLEXplus platform achieved temperature uniformity within ±0.5 °C, along with throughput advantages over competing solutions. This case underscores the critical importance of chuck sensor calibration in ensuring wafer test reliability and preventing yield loss.

This presentation describes a practical, high-efficiency ATE test methodology for ARM7-based chips, organized across three areas: hardware architecture, test efficiency optimization, and engineering deployment. At the hardware level, it covers the key elements required to build a robust test solution, including the selection of a high-speed test platform, full-link signal integrity simulation, and topology guidelines for PHY interface peripheral circuitry. It also introduces a coordinated signal integrity and power integrity optimization approach that addresses channel parameters such as insertion loss, return loss, and crosstalk, together with IR-drop control and PDN impedance shaping. Eye diagram and channel characterization are used to verify interconnect behavior under real test conditions, supported by high-bandwidth miniature switching schemes to improve loopback compactness and scalability. To improve test efficiency, the methodology applies a dynamic, adaptive test strategy guided by device behavior and workload conditions. Using established performance benchmarks such as Dhrystone MIPS, idle-to-max power analysis, max-power profiling, and memory throughput, it builds a multi-dimensional binning model—including DVFS-based binning—to better classify devices and focus test time where it adds the most value. Engineering-grade iterative techniques, including characterization (Char) testing and precise guard-band (GB) modeling, are also incorporated to expand parametric test coverage, with demonstrated improvements in coverage depth. For engineering deployment, the work presents a modular program approach that decouples test logic into reusable blocks and enables rapid adaptation across product variants, test stages (CP/FT), and tester platforms. It also introduces a closed-loop analysis workflow based on test vector compression and feature extraction to accelerate root-cause isolation and improve decision quality, as demonstrated by an optimized Fmax binning solution. The overall implementation path includes practical elements such as standardized log formats, yield correlation analysis, and end-to-end traceability to support reliable bring-up and production release.

Teradyne Sales and Marketing and external UltraFLEXplus customers have posed numerous questions to Teradyne Applications and Hardware Engineering regarding the Tester/Prober/Probe Card Z-Stack mechanical deflection performance of the Standard Probe Translation Layer (SPTL) vs. the newer Universal Probe Translation Layer (UPTL). As part of the UPTL release new probecard stiffeners that allowed increased application space were also developed. These new probecard stiffeners are available in Standard Application Area for SPTL/UPTL and Extended Application Area (EAA) for UPTL. Because the UPTL is a new interface and SAA stiffeners are compatible with both SPTL and UPTL numerous questions on the mechanical deflection performance of the multiple Z-Stack configurations possible with the new interface and stiffener. These questions were posed due to the fact that excess defection can cause continuity related issues and yield loss for applications that are sensitive to elevated probe card contact resistance caused by this deflection. To answer these questions a DOE was performed on multiple SPTL/UPTL SAA/EAA probe card combinations with probe forces up to 100kg. The deflection performance was characterized using specialized pins mounted on the probe head to facilitate measurement of the Z-Stack Actual Overtravel vs. Programmed Overtravel (AOT vs. POT) using the wafer prober.Electrical 1st to 100% continuity performance and electrical fill signature was also measured for the various UltraFLEXplus interface/stiffener/probe card combinations. The data collected was analyzed by overlaying the results of each set of tests to illustrate the comparative performance of the different hardware combinations. The presentation will provide internal and external customers to gain confidence in the UltraFLEXplus platform as well as provide insights on how data can be collected for future applications to ensure that there are no yield impacts with new, higher force, probe card applications and/or stiffener designs.